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Microchip Technology AT28C64X-25SI

Part No.:
AT28C64X-25SI
Manufacturer:
Microchip Technology
Category:
Memory
Package:
28-SOIC (0.295", 7.50mm Width)
Datasheet:
AetrixAT28C64X-25SI.pdf
Description:
IC EEPROM 64KBIT PARALLEL 28SOIC
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:1,353

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Product details

Overview

AT28C64X-25SI from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 250 ns read access time, 1 ms fast byte write cycle, and industrial temperature range (–40°C to +85°C). It operates from a single 5V ±10% supply, supports direct microprocessor control via READY/BUSY and DATA polling, and is used in firmware storage, configuration memory, and boot code retention for embedded controllers.

For engineers reviewing the AT28C64X-25SI datasheet, AT28C64X-25SI pinout, AT28C64X-25SI application, or AT28C64X-25SI equivalent, key selection criteria include its self-timed write architecture, CMOS/TTL compatibility, 10⁴ endurance cycles, RDY/BUSY signal omission (pin 1 NC), and support for chip erase and device identification via dedicated 32-byte memory region.

Technical Context

The AT28C64X-25SI implements a self-timed byte write cycle with internal address/data latches and automatic clear-before-write logic. Its RDY/BUSY output is not connected (NC at pin 1), requiring reliance on DATA polling (I/O7 complement detection) to determine write completion.

It uses CMOS process technology to achieve 30 mA active current and 100 µA standby current while maintaining TTL-compatible input thresholds (VIL = 0.8 V, VIH = 2.0 V) and output drive (VOL = 0.45 V at 2.1 mA). The device supports chip erase via 12 V on A9 and WE pulse, and includes 32 bytes of user-accessible identification memory at addresses 1FE0H–1FFFH.

Key Specifications

Parameter Value and Actual Design Meaning
Memory Size 64 Kbit (8,192 × 8 bits); sufficient for small boot loaders or configuration tables in resource-constrained systems.
Read Access Time 250 ns maximum; compatible with 4 MHz Z80 or 8 MHz 8051 bus timing without wait states.
Byte Write Time 1 ms typical; enables predictable firmware update latency without external timing circuitry.
Endurance 10,000 write/erase cycles; suitable for infrequent configuration updates, not high-frequency logging.
Data Retention 10 years at +85°C; validated for long-life industrial deployments without refresh.
Supply Voltage 5 V ±10%; eliminates need for precision voltage regulation in legacy 5 V systems.
Operating Temperature –40°C to +85°C; qualified for industrial control, automotive body electronics, and outdoor equipment.

Pinout & Package

AT28C64X-25SI is supplied in a 28-lead SOIC (Small Outline Integrated Circuit) package per JEDEC MS-012, 0.300" wide body, with gull-wing leads. Pin 1 is No Connect (NC), consistent with the "X" variant designation indicating RDY/BUSY functionality disabled.

Pin/Terminal Circuit Role Design Meaning
A0–A12 Address Inputs 13-bit address bus supporting full 8K-word addressing; compatible with 8086/8051 low-order address lines.
I/O0–I/O7 Bidirectional Data Bus 8-bit parallel interface; supports true read/write data transfer without direction control pins.
CE Chip Enable Active-low chip select; enables memory access only when asserted, allowing multi-chip decoding.
OE Output Enable Active-low output gate; controls data bus drivers independently of CE for bus contention management.
WE Write Enable Active-low write strobe; initiates self-timed byte write on falling edge with data latched on rising edge.
RDY/BUSY Open-Drain Status Output No connect (NC) on AT28C64X variants; write status must be monitored via DATA polling on I/O7.
VCC, GND Power Supply Single 5 V supply with decoupling required near pin 28 (VCC) and pin 14 (GND) per layout guidelines.

Key Features

Feature Design Value
Self-timed byte write Eliminates need for external write timing control; frees CPU bus during 1 ms internal clear-and-program sequence.
DATA polling (I/O7) Enables software-driven write completion detection without hardware interrupt or dedicated status pin.
Write protection logic Hardware-enforced inhibition below 3.8 V VCC and 5 ms power-on delay prevents spurious writes during brown-out.
Dedicated ID memory 32 bytes at 1FE0H–1FFFH allow unique device serialization or firmware version tagging without consuming main array space.
JEDEC byte-wide pinout Direct drop-in replacement for standard SRAM or EPROM sockets in legacy 28-pin DIP/SOIC designs.

Applications

Industrial PLC Configuration Storage Legacy PC BIOS Parameter Memory

Use Scenario: Storing I/O mapping, calibration coefficients, and alarm thresholds in programmable logic controllers deployed in factory automation.

IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during power-up and runtime reconfiguration; read-only during normal operation, written only during commissioning or maintenance.

Use Value: Ensures deterministic startup behavior after power loss and supports field-updatable parameters without requiring battery-backed SRAM.

Use Scenario: Retaining CMOS setup values (date/time, boot order, peripheral enables) in desktop motherboards using ISA or LPC bus interfaces.

IC Role / Device Role / Timing Role: Low-speed, infrequently written parameter store interfaced via ISA address/data bus and control signals (IOR#, IOW# mapped to OE/WE).

Use Value: Provides reliable, low-cost, pin-compatible alternative to Xicor/Xilinx NVSRAM in legacy PC platforms with 5 V logic rails.

Embedded Controller Boot Code Medical Device Calibration Data

Use Scenario: Holding minimal boot loader or FPGA configuration bitstream in safety-critical medical imaging subsystems.

IC Role / Device Role / Timing Role: Read-only execution memory during cold start; accessed sequentially by microcontroller's external memory interface at ≤4 MHz.

Use Value: Guarantees verified boot integrity across 10-year product lifecycle without risk of bit corruption under thermal cycling.

Use Scenario: Storing sensor offset/gain coefficients and regulatory compliance flags in portable diagnostic devices subject to ISO 13485 requirements.

IC Role / Device Role / Timing Role: Secure, tamper-evident nonvolatile storage written once during final test and read at every power-on self-test (POST).

Use Value: Meets traceability mandates via built-in 32-byte ID region, enabling audit-ready device serialization and calibration history.

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Alternative Part Technical Difference Application Difference Selection Advice
AT28C64B-25SI Same pinout and timing, but includes functional RDY/BUSY output (pin 1 active); higher endurance (10⁵ cycles) option available. Preferred where hardware handshaking simplifies firmware design; requires no change to PCB layout. Select AT28C64B-25SI if RDY/BUSY signal is needed; otherwise AT28C64X-25SI reduces external pull-up component count.
MX28F640JTI-25 Intel-compatible 64 Kbit flash; 250 ns read, but requires 12 V programming voltage and block erase (not byte-erasable). Suitable for firmware storage where infrequent full-image updates occur; incompatible with byte-level field updates. Choose MX28F640JTI-25 only if existing system already uses Intel flash protocol; AT28C64X-25SI offers superior byte-write flexibility.

Compared with AT28C64B-25SI, the AT28C64X-25SI trades RDY/BUSY functionality for simplified board-level design (no pull-up needed), while compared with MX28F640JTI-25, it delivers true random-byte write capability without block management overhead-critical for dynamic configuration storage.

Availability

AT28C64X-25SI is available at Aetrix Electronics and suitable for industrial control systems, legacy PC platform support, and embedded medical device manufacturing requiring stable component supply across extended production lifecycles.

Supply support for AT28C64X-25SI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.

The AT28C64X series was designed as a drop-in parallel EEPROM replacement for obsolete EPROMs and battery-backed SRAMs in industrial and computing applications requiring simple, robust, 5 V-only nonvolatile storage.

FAQ

What is the function of pin 1 on the AT28C64X-25SI?

Pin 1 on the AT28C64X-25SI is designated as No Connect (NC), meaning it is internally unconnected and must remain floating or tied to ground per layout best practices. This distinguishes the AT28C64X-25SI from the AT28C64B-25SI, which implements RDY/BUSY on pin 1. The AT28C64X-25SI relies exclusively on DATA polling via I/O7 for write completion detection.

Does the AT28C64X-25SI support chip erase, and how is it performed?

Yes, the AT28C64X-25SI supports chip erase. It is executed by applying 12.0 V ± 0.5 V to pin A9 while holding CE low and issuing a 10 ms low pulse on WE. During this operation, OE must be held high. The entire 8K × 8 memory array is set to 0xFF, and the 32-byte device ID region is also erased. This function is documented in the AT28C64X-25SI datasheet Section "Chip Clear".

How does write protection work on the AT28C64X-25SI?

The AT28C64X-25SI implements three-tiered hardware write protection: (1) VCC sense disables writes if supply drops below ~3.8 V; (2) a 5 ms internal power-on delay prevents writes during power ramp-up; and (3) write inhibit occurs if any of OE (high), CE (high), or WE (high) violates the required active-low assertion sequence. These mechanisms ensure the AT28C64X-25SI remains immune to accidental writes during noise events or brownouts.

Can the AT28C64X-25SI be used as a direct replacement for standard SRAM in existing designs?

Yes-the AT28C64X-25SI features JEDEC-approved byte-wide pinout and identical read-cycle timing to many 8K × 8 SRAMs (e.g., 6264), allowing direct socket replacement in systems where nonvolatility is added without redesign. However, write cycles require explicit WE control and take 1 ms, unlike SRAM's nanosecond writes; thus, firmware must implement polling or timing delays when writing to the AT28C64X-25SI.

What is the purpose of the 32-byte device identification memory in the AT28C64X-25SI?

The AT28C64X-25SI includes 32 bytes of dedicated EEPROM space at addresses 1FE0H–1FFFH, accessible using the same read/write protocol as main memory but requiring 12 V on A9 for write operations. This region enables permanent device serialization, firmware version stamping, or calibration data binding-providing traceability without consuming the primary 8K array used for application data storage.

AT28C64X-25SI Specifications

Product attributes
Attribute value
Manufacturer:
Microchip Technology
Series:
-
Package/Case:
28-SOIC (0.295", 7.50mm Width)
Packaging:
Tube
Product Status:
Obsolete
Programmable:
Not Verified
Memory Type:
Non-Volatile
Memory Format:
EEPROM
Technology:
EEPROM
Memory Size:
64Kbit
Memory Organization:
8K x 8
Memory Interface:
Parallel
Clock Frequency:
-
Write Cycle Time - Word, Page:
1ms
Access Time:
250 ns
Voltage - Supply:
4.5V ~ 5.5V
Operating Temperature:
-40°C ~ 85°C (TC)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
28-SOIC

AT28C64X-25SI FAQ

1.How can I place an order for AT28C64X-25SI through Aetrix?

Please submit a Request for Quotation (RFQ) for AT28C64X-25SI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT28C64X-25SI reliable?

The price and inventory of AT28C64X-25SI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C64X-25SI is usually 5 days.

3.What payment methods are accepted for AT28C64X-25SI?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C64X-25SI transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT28C64X-25SI?

AT28C64X-25SI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT28C64X-25SI order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT28C64X-25SI?

For technical support, including AT28C64X-25SI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C64X-25SI requirements.

6.How does Aetrix verify that AT28C64X-25SI is sourced from the original manufacturer or authorized distributors?

All AT28C64X-25SI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C64X-25SI meets industry standards.

7.What is the process for return or replacement of AT28C64X-25SI?

All AT28C64X-25SI units undergo pre-shipment inspection (PSI). If there is an issue with AT28C64X-25SI, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT28C64X-25SI part is unused and in its original packaging.

Return procedure for AT28C64X-25SI:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

AT28C64X-25SI Tags

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