Microchip Technology AT28HC256-12JU
- Part No.:
- AT28HC256-12JU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28HC256-12JU.pdf
- Description:
- IC EEPROM 256KBIT PAR 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:4,913
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256-12JU from Microchip Technology is a 256-Kbit (32,768 × 8) parallel EEPROM IC designed for nonvolatile data storage in industrial embedded systems. It features 70 ns read access time, 120 ns maximum access timing (−12 speed grade), 5V ±10% single-supply operation, JEDEC-standard byte-wide pinout, and supports both byte and 64-byte page write operations. It is commonly used in firmware parameter storage, calibration data retention, and configuration memory for programmable logic controllers.
For engineers reviewing the AT28HC256-12JU datasheet, AT28HC256-12JU pinout, AT28HC256-12JU application, or AT28HC256-12JU equivalent, key selection criteria include industrial temperature range (−40°C to +85°C), hardware/software data protection, DATA Polling and Toggle Bit write-completion detection, and compatibility with legacy SRAM-style bus interfaces without external timing logic.
Technical Context
The AT28HC256-12JU implements a CMOS-based EEPROM architecture with internal address/data latching for up to 64-byte page writes and an autonomous internal control timer. Its dual-line chip enable (CE) and output enable (OE) logic enables flexible bus contention management in shared-memory systems.
It integrates VCC-sense circuitry that inhibits writes below 3.8 V, a 5 ms power-on delay before write-enable, noise filtering on WE/CE inputs (<15 ns rejection), and optional software data protection using a 3-byte command sequence at fixed addresses (5555H/2AAAH/5555H). Device identification space (64 bytes at 7FC0H–7FFFH) is accessible via 12 V on A9.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32,768 × 8) - provides sufficient capacity for boot parameters, device IDs, and field-updatable configuration tables |
| Read Access Time | 120 ns max - ensures compatibility with 8 MHz Z80, 68K, and early ARM bus cycles without wait states |
| Page Write Cycle Time | 10 ms max - enables efficient bulk updates while maintaining deterministic worst-case latency |
| Endurance | 10,000 write/erase cycles - supports long-term field deployment in telemetry and industrial logging |
| Data Retention | 10 years at +85°C - guarantees integrity of stored calibration coefficients across product lifetime |
| Supply Voltage | 5 V ±10% - operates directly from standard TTL/CMOS logic rails without regulation overhead |
| Operating Temperature | −40°C to +85°C - certified for use in industrial automation, motor drives, and outdoor metering |
Pinout & Package
AT28HC256-12JU is supplied in a 32-lead PLCC (Plastic Leaded Chip Carrier) package with gull-wing leads, RoHS-compliant green molding compound, and JEDEC-standard pin assignment. Pin 1 is indexed by corner chamfer per Microchip Drawing C04-023 Rev C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32,768-word addressing; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface compatible with microprocessor data buses; supports true read/write without direction control pins |
| CE | Chip Enable | Active-low global select; must be low for read/write; high-Z output when asserted high |
| OE | Output Enable | Active-low output gate; allows CE-controlled chip selection while disabling outputs to prevent bus contention |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; initiates byte or page programming cycle |
| VCC | Power Supply | +5 V ±10% supply input; powers internal charge pumps and logic; includes VCC-sense write inhibit |
| GND | Ground Reference | Signal and power return path; decoupling required within 10 mm of VCC pin per layout guidelines |
| NC / DC | No Connect / Don't Connect | Pins 1 and 17 are unconnected; must remain floating-no routing or grounding permitted |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-Wide Pinout | Direct drop-in replacement for 27C256 EPROM and 62256 SRAM in existing PCB layouts |
| DATA Polling & Toggle Bit | Hardware-supported write completion detection via I/O7 complement or I/O6 toggling-eliminates need for fixed delays or external polling timers |
| 64-Byte Page Write | Reduces average write time by >90% vs. byte-by-byte programming-critical for real-time configuration saves |
| Software Data Protection | User-configurable lock/unlock via 3-byte command sequence at 5555H/2AAAH/5555H-prevents accidental overwrites during power transitions |
| 12 V Device ID Access | 64-byte dedicated ID space (7FC0H–7FFFH) accessible only with 12 V on A9-enables secure serialization and traceability |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Memory |
|---|---|
Use Scenario: Storing user-modified I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via parallel bus during startup and runtime reconfiguration. Use Value: Ensures parameter persistence across 100,000+ power cycles and 10-year shelf life without battery backup. | Use Scenario: Retaining sensor calibration coefficients, patient-specific therapy settings, and regulatory audit logs in portable infusion pumps and diagnostic monitors. IC Role / Device Role / Timing Role: Secure, tamper-resistant memory block isolated from main processor flash; accessed only during calibration routines. Use Value: Meets IEC 62304 Class B requirements for data integrity with hardware write inhibit and voltage-monitored programming. |
| Automotive ECU Parameter Tables | Test Equipment Firmware Patch Storage |
Use Scenario: Holding adaptive learning values (e.g., fuel trim, idle air control offsets) and regional emission map variants in engine control units. IC Role / Device Role / Timing Role: Parallel-mapped memory region updated infrequently but requiring guaranteed write endurance and thermal stability. Use Value: Industrial temperature rating and 10,000-cycle endurance support repeated field recalibration under under-hood thermal stress. | Use Scenario: Storing hot-fix patches, instrument-specific calibration deltas, and protocol stack updates in automated test equipment without requiring full FPGA or MCU reflash. IC Role / Device Role / Timing Role: Field-upgradable code/data overlay memory accessed via dedicated address window during service mode. Use Value: Enables zero-downtime firmware corrections using standard JTAG or UART host interface-no reprogramming fixtures needed. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-12JU | Same pinout and function; differs only in endurance (100k cycles vs. 10k) and write cycle time (3 ms vs. 10 ms) | Preferred where frequent field updates are required (e.g., data loggers); not necessary for static configuration storage | Select AT28C256-12JU only if >10k write cycles are confirmed in system usage profile |
| MX28F256J3F-12JN | Intel-compatible 28F-series Flash; requires sector erase before write; no built-in DATA Polling | Suitable for firmware storage but unsuitable for dynamic parameter updates due to erase latency and lack of byte-write capability | Choose only when migrating legacy Flash-based designs; requires significant firmware changes to manage erase blocks |
Compared with AT28HC256-12JU, AT28C256-12JU offers faster writes and higher endurance at identical pinout and voltage, while MX28F256J3F-12JN trades byte-level flexibility for higher density and lower cost per bit-but mandates erase-before-write and lacks hardware write-status signaling.
Availability
AT28HC256-12JU is available at Aetrix Electronics and suitable for industrial PLCs, medical instrumentation, automotive ECUs, and automated test equipment requiring stable component supply across extended production lifecycles.
Supply support for AT28HC256-12JU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and nonvolatile memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The AT28HC256 belongs to Microchip's industrial-grade parallel EEPROM product line, engineered for reliable, low-power, SRAM-compatible nonvolatile storage in harsh environments where data integrity and long-term retention are critical.
FAQ
What is the maximum operating temperature range for the AT28HC256-12JU?
The AT28HC256-12JU is rated for industrial temperature operation from −40°C to +85°C. This range is validated per Microchip's DS20006428B datasheet Section 4.2 and applies to all DC and AC electrical characteristics including read access time (120 ns), standby current (≤3 mA), and write cycle timing. Operation outside this range may result in undefined behavior or reduced endurance.
Does the AT28HC256-12JU require external high-voltage programming circuitry?
No, the AT28HC256-12JU performs all internal charge pumping and programming voltage generation from its single 5 V ±10% supply. High-voltage (12 V) is required only for accessing the 64-byte device identification area (7FC0H–7FFFH) via A9-standard read/write operations use only VCC. No external VPP generator or programming adapter is needed.
How does DATA Polling work on the AT28HC256-12JU during a write cycle?
During a write cycle, reading the last written byte returns the complement of that data on I/O7. Once the internal programming completes, I/O7 outputs the true data value. This allows the host processor to poll I/O7 in a tight loop without fixed delays-reducing software overhead and ensuring deterministic write completion detection for the AT28HC256-12JU.
Can the AT28HC256-12JU be used as a direct replacement for the AT27C256 EPROM?
Yes-the AT28HC256-12JU uses the same JEDEC-standard 28-pin SOIC and 32-pin PLCC footprints and pinout as the AT27C256 EPROM, including identical address, data, CE, OE, and WE assignments. Unlike EPROMs, it requires no UV erasure and supports in-system reprogramming, making it a functional and physical drop-in upgrade for legacy designs using AT27C256-12JU.
What is the purpose of pins 1 and 17 labeled "DC" on the AT28HC256-12JU PLCC package?
Pins 1 and 17 on the AT28HC256-12JU PLCC package are designated "Don't Connect" (DC) and must remain electrically unconnected-no routing, grounding, or capacitive loading is permitted. These pins are internally unused and floating; connecting them may cause unpredictable behavior or violate Microchip's qualified reliability testing conditions per DS20006428B Section 2.
AT28HC256-12JU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28HC256-12JU FAQ
1.How can I place an order for AT28HC256-12JU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256-12JU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256-12JU reliable?
The price and inventory of AT28HC256-12JU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256-12JU is usually 5 days.
3.What payment methods are accepted for AT28HC256-12JU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256-12JU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256-12JU?
AT28HC256-12JU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256-12JU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256-12JU?
For technical support, including AT28HC256-12JU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256-12JU requirements.
6.How does Aetrix verify that AT28HC256-12JU is sourced from the original manufacturer or authorized distributors?
All AT28HC256-12JU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256-12JU meets industry standards.
7.What is the process for return or replacement of AT28HC256-12JU?
All AT28HC256-12JU units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256-12JU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256-12JU part is unused and in its original packaging.
Return procedure for AT28HC256-12JU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256-12JU Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

