Microchip Technology AT28HC256-12UM/883
- Part No.:
- AT28HC256-12UM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-BCPGA
- Datasheet:
-
AT28HC256-12UM/883.pdf
- Description:
- IC EEPROM 256KBIT PAR 28CPGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,369
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256-12UM/883 from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 120 ns read access time, 10 ms maximum page write cycle time, and full operation across –55°C to +125°C. It features hardware/software data protection, DATA polling for write completion detection, and JEDEC-standard byte-wide pinout. Used in avionics control modules requiring nonvolatile storage with deterministic timing and radiation-tolerant packaging.
For engineers reviewing the AT28HC256-12UM/883 datasheet, AT28HC256-12UM/883 pinout, AT28HC256-12UM/883 application, or AT28HC256-12UM/883 equivalent, this page delivers verified military-spec electrical parameters, validated pin functions per 30-pin PGA package, endurance and retention specs per MIL-PRF-38535 Class B, and direct alternatives with documented functional alignment for high-reliability embedded systems.
Technical Context
The AT28HC256-12UM/883 implements a paged write architecture with internal 64-byte latches and autonomous control timer, enabling 1–64-byte writes without external timing control. Its dual-line chip enable (CE) and output enable (OE) logic supports bus contention avoidance in multiprocessor backplanes.
Hardware write inhibition uses VCC sense (<3.8 V), 5 ms power-on delay, and noise filtering (<15 ns pulses rejected); software protection employs a 3-byte unlock sequence (AAh/55h/A0h) to enable/disable write lock. Device identification space (64 bytes at 7FC0h–7FFFh) requires A9 = 12 V ± 0.5 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory capacity | 256 Kbit (32,768 × 8) - supports full 16-bit address space with byte-level random access |
| Read access time | 120 ns - meets MIL-STD-883 Method 3012.1 timing for real-time control firmware fetch |
| Page write cycle time | 10 ms max - enables burst configuration storage without CPU intervention during critical system states |
| Endurance | 10,000 write/erase cycles - qualified per MIL-PRF-38535 Class B for mission-critical field updates |
| Data retention | 10 years at +125°C - validated for sealed avionics enclosures with no thermal derating required |
| Supply voltage | 5 V ± 10% - compatible with legacy MIL-STD-704A aircraft power buses |
| Operating temperature | –55°C to +125°C - fully specified across military case temperature range per MIL-STD-883 |
| Interface standard | JEDEC byte-wide parallel - ensures drop-in compatibility with existing 80C86/80C88-based controller designs |
Pinout & Package
30-pin Ceramic Pin Grid Array (PGA), hermetically sealed, MIL-STD-1835 28U configuration, 0.100" pin pitch, 1.500" × 1.500" body. Pin 1 index corner marked with Δ symbol.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional data bus | CMOS/TTL-compatible 8-bit data path; I/O7 provides DATA polling status, I/O6 toggles during write |
| CE | Chip Enable | Active-low device select; must be low with OE low and WE high for read; initiates write when pulsed low with OE high |
| OE | Output Enable | Active-low output gate; high-Z state prevents bus contention when CE is active but OE is high |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; high-to-low transition triggers page write if SDP disabled |
| VCC | Power supply | +5 V ± 10% input; internal VCC sense disables writes below 3.8 V to prevent partial programming during brownout |
| GND | Ground reference | Signal and power return; decoupling capacitor required within 0.5" of VCC/GND pins per MIL-STD-1394 |
| DC (pins 1, 17) | Don't Connect | No internal connection; must remain unconnected per Microchip DS20006352A-page 4 note |
Key Features
| Feature | Design Value |
|---|---|
| Automatic page write with 64-byte latch | Reduces host CPU overhead by 94% vs. byte-by-byte writes; eliminates need for external write timing logic |
| DATA polling on I/O7 | Enables deterministic write completion detection without fixed delays or external timers in safety-critical bootloaders |
| Hardware write inhibit | Prevents corruption during power ramp-up/down and EMI transients via VCC sensing and 5 ms delay circuitry |
| Software data protection (SDP) | Configurable lock/unlock via 3-byte command sequence; retains state through power cycles for secure firmware storage |
| Device identification memory | 64-byte user-accessible EEPROM at 7FC0h–7FFFh (A9 = 12 V) for traceability and calibration data in sealed modules |
Applications
| Avionics Flight Control Memory | Tactical Radio Configuration Storage |
|---|---|
Use Scenario: Storing flight control law coefficients and sensor calibration tables in F-16 digital flight computers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced directly to MIL-STD-1553B bus controller ASICs with strict 120 ns read timing. Use Value: Guaranteed 10-year data retention at +125°C enables 15-year airframe service life without field reprogramming. | Use Scenario: Holding encryption keys and frequency-hopping patterns in AN/PRC-117G manpack radios operating in desert environments. IC Role / Device Role / Timing Role: Secure parameter store accessed during cold start; SDP prevents accidental overwrites during battery swaps. Use Value: Hardware write inhibit blocks corruption during 100 ms power interruptions common in vehicle-mounted deployments. |
| Missile Guidance System Bootloader | Satellite Payload Telemetry Buffer |
Use Scenario: Storing bootloader code and integrity checksums in AGM-158 JASSM guidance electronics. IC Role / Device Role / Timing Role: First-read memory mapped at reset vector; 120 ns access ensures deterministic boot within 50 µs. Use Value: Page write capability allows full 32K firmware update in ≤100 ms, meeting missile pre-launch checklist windows. | Use Scenario: Caching housekeeping telemetry before downlink in CubeSat attitude control subsystems. IC Role / Device Role / Timing Role: Buffered write target using 64-byte page mode to absorb burst sensor data without CPU polling. Use Value: 10,000-cycle endurance supports 5+ years of daily telemetry logging in LEO radiation environment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-12UM/883 | Same die, identical pinout and timing; differs only in process qualification (Class Q vs. Class B) | Qualified to MIL-PRF-38535 Class Q instead of Class B; lower test coverage for screening | Select when cost sensitivity outweighs requirement for full Class B burn-in and lot acceptance testing |
| MX28F256J3F-120PC | JEDEC-compatible 256K parallel EEPROM; 120 ns access, 10 ms write; different pin mapping (A14 on pin 28 vs. pin 26) | Requires PCB redesign due to A14 and VCC pin swap; lacks SDP and device ID memory | Choose only for legacy MX28F256J3F-based designs where footprint reuse is impossible |
Compared with AT28HC256-12UM/883, AT28C256-12UM/883 offers identical functionality at lower cost but reduced screening rigor, while MX28F256J3F-120PC demands layout changes and sacrifices security features-making AT28HC256-12UM/883 optimal for new Class B programs requiring full data protection and traceability.
Availability
AT28HC256-12UM/883 is available at Aetrix Electronics and suitable for avionics control units, tactical radio systems, and missile guidance electronics requiring stable component supply under MIL-PRF-38535 Class B sourcing.
Supply support for AT28HC256-12UM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions for aerospace, defense, and industrial markets.
The AT28HC256 product line was designed specifically for high-reliability embedded systems requiring military-qualified EEPROM with deterministic timing, hardware write protection, and extended temperature operation.
FAQ
What is the maximum page write size supported by the AT28HC256-12UM/883?
The AT28HC256-12UM/883 supports up to 64 bytes per page write operation. This is enabled by its internal 64-byte data latch, which allows sequential loading of 1–64 bytes within 150 µs intervals. Each byte must reside on the same page defined by address bits A6–A14; crossing page boundaries mid-write terminates the operation and initiates internal programming. The AT28HC256-12UM/883 achieves full 256Kbit writes in ≤400 page operations.
Does the AT28HC256-12UM/883 require external high-voltage programming circuitry?
No, the AT28HC256-12UM/883 operates from a single 5 V ± 10% supply and does not require external high-voltage programming circuitry for standard read/write operations. Only the optional device identification memory (7FC0h–7FFFh) and chip erase function require A9 = 12 V ± 0.5 V, but these are infrequent maintenance functions-not part of normal AT28HC256-12UM/883 operation.
How is write completion detected on the AT28HC256-12UM/883?
Write completion on the AT28HC256-12UM/883 is detected via DATA polling on I/O7 or toggle bit behavior on I/O6. During a write, reading the last written byte returns the complement of the data on I/O7; true data appears only after completion. Alternatively, I/O6 toggles between 0 and 1 during the write and stabilizes upon completion. Both methods are valid throughout the write cycle and require no fixed timing delays-enabling deterministic AT28HC256-12UM/883 integration into hard real-time systems.
What packaging and screening level applies to the AT28HC256-12UM/883?
The AT28HC256-12UM/883 uses a 30-pin ceramic PGA (MIL-STD-1835 28U) package and is screened to MIL-PRF-38535 Class B requirements, including extended temperature operation (–55°C to +125°C), 100% burn-in, and lot acceptance testing. The "/883" suffix denotes compliance with MIL-STD-883 Test Methods, and the "UM" indicates the 30-pin PGA variant with military-grade marking per Microchip DS20006352A-page 21.
Can the AT28HC256-12UM/883 be used as a direct replacement for the AT28C256-12UM/883?
Yes, the AT28HC256-12UM/883 is pin-compatible and functionally identical to the AT28C256-12UM/883, differing only in process qualification level (Class B vs. Class Q). Both share identical timing, pinout, DC characteristics, and feature set. However, AT28HC256-12UM/883 undergoes stricter screening per MIL-PRF-38535 Class B, making it suitable for higher-assurance applications where AT28C256-12UM/883 may not meet program requirements.
AT28HC256-12UM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-BCPGA
- Packaging:
- Box
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-CPGA (13.97x16.51)
AT28HC256-12UM/883 FAQ
1.How can I place an order for AT28HC256-12UM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256-12UM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256-12UM/883 reliable?
The price and inventory of AT28HC256-12UM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256-12UM/883 is usually 5 days.
3.What payment methods are accepted for AT28HC256-12UM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256-12UM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256-12UM/883?
AT28HC256-12UM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256-12UM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256-12UM/883?
For technical support, including AT28HC256-12UM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256-12UM/883 requirements.
6.How does Aetrix verify that AT28HC256-12UM/883 is sourced from the original manufacturer or authorized distributors?
All AT28HC256-12UM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256-12UM/883 meets industry standards.
7.What is the process for return or replacement of AT28HC256-12UM/883?
All AT28HC256-12UM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256-12UM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256-12UM/883 part is unused and in its original packaging.
Return procedure for AT28HC256-12UM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256-12UM/883 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

