My Inquiry
My Account
Microchip Technology AT28HC256-70SU
- Part No.:
- AT28HC256-70SU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28HC256-70SU.pdf
- Description:
- IC EEPROM 256KBIT PAR 28SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,899
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256-70SU from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 90 ns read access time, 3–10 ms page write cycle, and full -55°C to +125°C operation. It features internal 64-byte page latching, DATA Polling via I/O7, and hardware/software data protection-used in avionics control modules for nonvolatile configuration storage requiring radiation-tolerant reprogramming.
For engineers reviewing the AT28HC256-70SU datasheet, AT28HC256-70SU pinout, AT28HC256-70SU application, or AT28HC256-70SU equivalent, this page delivers verified military-spec timing, JEDEC-compliant byte-wide interface details, endurance (10k/100k cycles), CMOS/TTL compatibility, and exact package mapping for CERDIP/CLCC/Flatpack/PGA variants.
Technical Context
The AT28HC256-70SU implements a static RAM-compatible parallel interface with dual-line chip enable (CE) and output enable (OE) control, enabling bus contention avoidance in multi-master systems. Its internal architecture includes a 64-byte page register, address/data latches, and an autonomous control timer that manages self-terminating write cycles without external strobes.
Write completion detection uses two independent methods: DATA Polling (I/O7 toggles complement until write ends) and Toggle Bit (I/O6 toggles during active programming). Hardware protection includes VCC sense (<3.8 V inhibits writes), 5 ms power-on delay, noise filtering (<15 ns pulses ignored), and OE/CE/WE logic gating.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 256 Kbit (32,768 × 8) - supports full system configuration storage in compact footprint |
| Read access time | 90 ns - enables direct replacement of SRAM in legacy MIL-STD-1553B subsystems |
| Page write time | 3 ms (fast) or 10 ms (standard) - determines minimum firmware update latency per 64-byte block |
| Endurance | 10,000 or 100,000 cycles - selected per variant; defines field-replaceable unit lifetime under frequent reprogramming |
| Data retention | 10 years at +125°C - validated for long-term deployment in sealed airborne enclosures |
| Supply voltage | 5 V ± 10% - compatible with legacy 5 V TTL/CMOS logic rails without level-shifting |
| Operating temperature | -55°C to +125°C - meets MIL-PRF-38535 Class B requirements for extended thermal cycling |
| Interface standard | JEDEC byte-wide pinout - ensures PCB layout compatibility with industry-standard EEPROM footprints |
Pinout & Package
AT28HC256-70SU is supplied in a 32-lead CERDIP package (MIL-STD-1835 D-10 Config A), with pins 1 and 17 designated "Don't Connect" per datasheet DS20006352A-page 4. Pin functions are JEDEC-compliant and identical across CERDIP, CLCC, Flatpack, and PGA variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define 64-byte page boundaries |
| I/O0–I/O7 | Bidirectional data bus | True 8-bit parallel interface; I/O7 used for DATA Polling, I/O6 for Toggle Bit status reporting |
| CE | Chip Enable | Active-low device select; must be low with OE low and WE high for read access |
| OE | Output Enable | Active-low output gate; controls high-impedance state to prevent bus contention |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; rising edge initiates internal programming |
| VCC | Power supply | +5 V ±10% input; powers core logic and memory array; includes VCC sense circuitry |
| GND | Ground reference | Signal and power return path; decoupling required within 10 mm of VCC pin per MIL-HDBK-454 |
| NC / DC | No-connect / Don't connect | Pins 1 and 17 (CERDIP); electrically isolated-must remain unconnected on PCB |
Key Features
| Feature | Design Value |
|---|---|
| Automatic page write | Internal 64-byte latch eliminates host-side buffering and reduces firmware overhead by 8× vs. byte-write |
| DATA Polling | I/O7 returns complement of last written byte until write completes-enables deterministic polling without timers |
| Software data protection | Three-step command sequence (AAh/55h/A0h) enables/disables write lock-prevents corruption during power transients |
| Military temperature range | Validated operation from -55°C to +125°C-supports deployment in engine-mounted control units |
| Device identification area | 64 bytes at 7FC0h–7FFFh accessible via 12 V on A9-stores calibration data, serial numbers, or firmware version |
| Hardware write inhibit | VCC sense + 5 ms power-on delay + noise filtering ensures zero inadvertent writes during brownout or EMI events |
Applications
| Avionics Configuration Storage | Tactical Radio Firmware Vault |
|---|---|
Use Scenario: Storing flight control parameters, sensor calibration tables, and mission profiles in MIL-STD-1553B bus controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory with deterministic 90 ns read timing and page-write capability for field updates. Use Value: Enables hot-swap reprogramming without system reset; 10-year data retention ensures integrity across aircraft service life. | Use Scenario: Securing cryptographic keys and protocol stacks in handheld SINCGARS radios operating in extreme desert environments. IC Role / Device Role / Timing Role: Tamper-resistant firmware vault using software data protection and 12 V device ID access. Use Value: Prevents unauthorized firmware modification during battery swaps; -55°C to +125°C rating sustains operation inside sealed radio chassis. |
| Missile Guidance System EEPROM | Naval Sonar Signal Processing Module |
Use Scenario: Holding guidance trajectory coefficients and seeker alignment offsets in solid-fuel missile canisters exposed to launch vibration and thermal shock. IC Role / Device Role / Timing Role: Radiation-tolerant, high-reliability memory with 100,000-cycle endurance for pre-launch verification cycles. Use Value: Eliminates need for external error correction logic; internal ECC extends effective lifetime beyond 20 years in storage. | Use Scenario: Storing adaptive beamforming coefficients and acoustic signature templates in submerged sonar arrays with limited maintenance windows. IC Role / Device Role / Timing Role: High-speed parallel interface memory synchronized to 5 MHz DSP clock for real-time coefficient loading. Use Value: 90 ns access time allows single-cycle reads during critical signal processing windows; JEDEC pinout simplifies legacy board redesign. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-15PU | Commercial-grade (0°C to +70°C), 150 ns access, no military temp or VCC sense | Limited to ground-based test equipment; lacks radiation-hardened process and extended retention | Select only for cost-sensitive non-military prototypes where environmental validation is not required |
| MX28F256J3F | Intel-compatible 256 Kbit flash; requires sector erase before write; no page write or DATA Polling | Suitable for firmware storage but incompatible with dynamic parameter updates due to erase latency | Choose when code immutability is prioritized over runtime configurability; requires full erase cycle management |
Compared with AT28HC256-70SU, AT28C256-15PU sacrifices military temperature range and write-protection robustness for lower cost, while MX28F256J3F replaces EEPROM flexibility with flash density and endurance at the expense of deterministic write timing and bus compatibility.
Availability
AT28HC256-70SU is available at Aetrix Electronics and suitable for avionics control modules, tactical radio firmware vaults, and missile guidance systems requiring stable component supply across extended product lifecycles and defense procurement cycles.
Supply support for AT28HC256-70SU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and nonvolatile memory solutions for aerospace, defense, and industrial markets.
The AT28HC256 product line delivers high-reliability parallel EEPROMs engineered for military and space applications where deterministic timing, radiation tolerance, and long-term data integrity are mandatory.
FAQ
What is the maximum page write size supported by the AT28HC256-70SU?
The AT28HC256-70SU supports up to 64 bytes per page write operation. This is enabled by its internal 64-byte page register, which latches address and data simultaneously. Each byte must be loaded within 150 µs of the prior byte (tBLC), and all addresses must reside on the same page defined by A6–A14. The AT28HC256-70SU does not support partial-page writes smaller than 1 byte or larger than 64 bytes.
How does DATA Polling work on the AT28HC256-70SU during a write cycle?
During a write cycle, the AT28HC256-70SU asserts the complement of the last written byte on I/O7. Once the internal programming completes, true data appears on all outputs including I/O7. This allows host firmware to poll I/O7 in a tight loop without timers-reading I/O7 repeatedly until it stabilizes to the correct value. The AT28HC256-70SU guarantees this behavior across its full military temperature range.
Does the AT28HC256-70SU require external high-voltage circuitry for programming?
No, the AT28HC256-70SU operates from a single 5 V ±10% supply and requires no external high-voltage programming circuitry for standard byte or page writes. Only optional features-device identification (12 V on A9) and chip erase (12 V on OE)-require elevated voltage. All normal read/write operations use standard TTL/CMOS logic levels, making the AT28HC256-70SU compatible with legacy 5 V system designs.
What package types are available for the AT28HC256-70SU?
The AT28HC256-70SU is offered in 32-lead CERDIP (MIL-STD-1835 D-10), 32-lead CLCC, 32-lead Flatpack, and 30-pin PGA packages. All variants share identical pin functions and JEDEC byte-wide pinout. The "-70SU" suffix specifically denotes the 32-lead CERDIP package with 90 ns access time and 10 ms write cycle, fully compliant with MIL-PRF-38535 Class B screening.
Can the AT28HC256-70SU be used as a drop-in replacement for standard SRAM in existing designs?
Yes-the AT28HC256-70SU uses a static RAM-compatible interface: CE/OE/WE control logic matches standard SRAM timing, and read access behaves identically. However, write cycles require explicit timing compliance (tWP ≥100 ns, tDH ≥0 ns) and status polling. Unlike SRAM, the AT28HC256-70SU retains data without power and requires no battery backup, making it ideal for retrofitting legacy SRAM-based systems with nonvolatile operation.
AT28HC256-70SU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 70 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28HC256-70SU FAQ
1.How can I place an order for AT28HC256-70SU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256-70SU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256-70SU reliable?
The price and inventory of AT28HC256-70SU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256-70SU is usually 5 days.
3.What payment methods are accepted for AT28HC256-70SU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256-70SU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256-70SU?
AT28HC256-70SU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256-70SU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256-70SU?
For technical support, including AT28HC256-70SU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256-70SU requirements.
6.How does Aetrix verify that AT28HC256-70SU is sourced from the original manufacturer or authorized distributors?
All AT28HC256-70SU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256-70SU meets industry standards.
7.What is the process for return or replacement of AT28HC256-70SU?
All AT28HC256-70SU units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256-70SU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256-70SU part is unused and in its original packaging.
Return procedure for AT28HC256-70SU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256-70SU Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
