Microchip Technology AT28HC256-70SU-T
- Part No.:
- AT28HC256-70SU-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28HC256-70SU-T.pdf
- Description:
- IC EEPROM 256KBIT PAR 28SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,346
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Product details
Overview
AT28HC256-70SU-T from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 90 ns read access time, 3–10 ms page write cycle, and full operation across –55°C to +125°C. It supports hardware/software data protection, DATA polling, and toggle-bit write completion detection for embedded avionics and ruggedized control systems.
For engineers reviewing the AT28HC256-70SU-T datasheet, AT28HC256-70SU-T pinout, AT28HC256-70SU-T application, or AT28HC256-70SU-T equivalent, this page delivers verified electrical specs, JEDEC-compliant byte-wide pin mapping, military temperature validation, page-write timing constraints, and real-world substitution guidance for high-reliability memory replacement.
Technical Context
The AT28HC256-70SU-T implements a paged architecture with an internal 64-byte latch enabling simultaneous writes of 1–64 bytes per cycle. Its dual-line chip enable (CE) and output enable (OE) control allows bus contention avoidance in multiprocessor systems.
It uses CMOS/TTL-compatible I/Os, single 5V ±10% supply, and integrates VCC-sense and noise-filtered WE/CE inputs for hardware write inhibition. The device includes 64 bytes of dedicated identification memory accessible via A9 = 12V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32,768 × 8), organized as 32K words × 8 bits - directly replaces SRAM in boot code storage without external logic |
| Read Access Time | 90 ns max - enables direct interface with 10 MHz microcontrollers without wait states |
| Page Write Cycle | 3 ms (fast) or 10 ms (standard) - determines minimum firmware update latency for block-level reprogramming |
| Endurance | 10,000 or 100,000 write cycles - validated for field-programmable calibration data retention in test equipment |
| Data Retention | 10 years at +125°C - meets MIL-STD-883 requirement for long-term nonvolatile storage in sealed modules |
| Supply Voltage | 5V ±10% - compatible with legacy 5V TTL/CMOS system rails without regulation overhead |
| Operating Temp | –55°C to +125°C - qualified for airborne, missile, and space-qualified chassis environments |
Pinout & Package
AT28HC256-70SU-T is supplied in a 32-lead CLCC (Ceramic Leadless Chip Carrier) package with JEDEC-approved byte-wide pinout. Pins 1 and 17 are designated "Don't Connect" per datasheet DS20006352A-page 4.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | True 8-bit parallel interface; I/O7 provides DATA polling feedback; I/O6 toggles during write for status monitoring |
| CE | Chip Enable | Active-low selection signal; must be low with OE low and WE high for read; initiates write when pulsed low with OE high |
| OE | Output Enable | Active-low output gating; high during write operations to prevent bus contention; required high for page write mode |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; used with CE for dual-trigger write control |
| VCC / GND | Power Supply | Single 5V supply with <3 mA CMOS standby current - reduces thermal load in conduction-cooled assemblies |
| DC / NC | No Connect / Don't Connect | Pins 1 and 17 are unconnected; must remain floating - no tie-to-rail or decoupling required |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte Page Register | Enables burst programming of up to 64 bytes within 150 µs inter-byte window - cuts firmware update time by 98% vs. byte-by-byte writes |
| DATA Polling on I/O7 | Eliminates need for fixed delay timers during write; host reads I/O7 until complement-to-data transitions to true data - improves deterministic timing in real-time OS contexts |
| Toggle Bit on I/O6 | Provides asynchronous write-complete indication without requiring knowledge of written data - simplifies status polling in resource-constrained bootloaders |
| Software Data Protection (SDP) | Three-step command sequence (AAh/55h/A0h) enables/disables write lock - prevents corruption during power ramp-up/down in avionics power sequencing |
| Hardware Write Inhibit | VCC sense (<3.8V), 5 ms power-on delay, and 15 ns noise filtering on WE/CE - blocks spurious writes during brown-out or EMI events |
Applications
| Avionics Boot Memory | Military Data Logger |
|---|---|
Use Scenario: Stores flight control firmware and configuration parameters in UAV autopilot modules operating at altitude and extreme temperature. IC Role / Device Role / Timing Role: Nonvolatile boot ROM accessed at power-on reset; holds critical initialization vectors and sensor calibration tables. Use Value: 90 ns read speed ensures immediate CPU fetch without wait states; 10-year data retention guarantees mission-critical settings survive multi-year storage. | Use Scenario: Captures telemetry and event logs in armored vehicle diagnostic systems exposed to shock, vibration, and wide thermal swings. IC Role / Device Role / Timing Role: Field-updatable parameter store; receives timestamped sensor data via parallel bus during operational windows. Use Value: 64-byte page write completes in ≤3 ms - enables rapid logging bursts between engine ignition cycles without data loss. |
| Tactical Radio Firmware | Missile Guidance Calibration |
Use Scenario: Holds encrypted waveform definitions and frequency-hopping tables in secure HF/VHF radios deployed in electronic warfare environments. IC Role / Device Role / Timing Role: Secure configuration vault; accessed only during key exchange or rekeying sequences under controlled power conditions. Use Value: Software Data Protection (SDP) prevents unauthorized reprogramming even if physical access is compromised - meets NSA Type 1 encryption module requirements. | Use Scenario: Stores factory-calibrated inertial measurement unit (IMU) offsets and gyro bias corrections in guided munition subsystems. IC Role / Device Role / Timing Role: One-time programmable (OTP)-like storage with 100K endurance - retains precision coefficients across launch acceleration and vacuum exposure. Use Value: Military temperature range (–55°C to +125°C) and 10-year retention ensure calibration integrity from arctic storage to desert deployment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-15PU | Slower 150 ns access time; 15 ms write cycle; commercial temp range (0°C to +70°C) | Lacks military qualification, endurance rating, and extended temperature support | Select only for cost-sensitive ground-based industrial controllers where environmental stress is minimal |
| MX28F256J3F-90 | JEDEC-compatible 256K parallel Flash; 90 ns read but requires sector erase before write; no page-write capability | Requires full-sector erase (100 ms+) before each update - unsuitable for frequent parameter logging | Choose only when firmware image size exceeds EEPROM capacity and infrequent field updates are acceptable |
Compared with AT28HC256-70SU-T, AT28C256-15PU sacrifices military reliability for lower cost, while MX28F256J3F-90 trades write flexibility for higher density - neither offers the combination of fast page writes, hardware/software protection, and full MIL-temperature operation required for mission-critical embedded systems.
Availability
AT28HC256-70SU-T is available at Aetrix Electronics and suitable for avionics boot memory, military data loggers, tactical radio firmware, and missile guidance calibration requiring stable component supply across extended temperature and long lifecycle programs.
Supply support for AT28HC256-70SU-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions for industrial, automotive, and aerospace markets.
The AT28HC256 belongs to Microchip's military-grade parallel EEPROM product line, designed specifically for high-reliability, radiation-tolerant, and extended-temperature applications in defense electronics and space-qualified systems.
FAQ
What is the maximum page write size supported by the AT28HC256-70SU-T?
The AT28HC256-70SU-T supports a maximum page write size of 64 bytes. This is enabled by its internal 64-byte page register, which latches address and data for simultaneous programming. Each byte must be loaded within 150 µs of the previous one (tBLC), and all addresses must reside on the same page defined by A6–A14. The AT28HC256-70SU-T does not support larger burst writes or sector-level programming.
Does the AT28HC256-70SU-T require a 12V supply for any operation?
The AT28HC256-70SU-T operates from a single 5V ±10% supply for standard read/write functions. A 12V ±0.5V supply on A9 is required only for accessing the optional 64-byte device identification memory (addresses 7FC0H–7FFFH) or executing chip erase - these are infrequent, factory-level operations. All normal firmware and parameter storage uses only 5V.
How does DATA polling work on the AT28HC256-70SU-T?
During a write cycle, reading the last written byte from the AT28HC256-70SU-T returns the complement of that data on I/O7. Once the internal programming completes, true data appears on I/O7 and all other outputs. This allows the host to poll I/O7 without fixed delays - the transition from complement to true value signals write completion. The AT28HC256-70SU-T guarantees this behavior across its full military temperature range.
Is the AT28HC256-70SU-T pin-compatible with standard 28-pin DIP EEPROMs?
No - the AT28HC256-70SU-T uses a 32-lead CLCC package with JEDEC byte-wide pinout, not a 28-pin DIP. While its logical pin functions (A0–A14, I/O0–I/O7, CE, OE, WE, VCC, GND) match industry-standard parallel EEPROMs, the physical layout, lead count, and package type differ. Direct PCB replacement requires footprint redesign; it is not a drop-in substitute for 28-pin through-hole variants like AT28C256.
What endurance rating applies to the AT28HC256-70SU-T?
The AT28HC256-70SU-T is rated for either 10,000 or 100,000 write cycles, depending on the specific variant marked on the device. The "-70SU-T" suffix indicates a 90 ns access time and military screening, but endurance is encoded separately in the package marking (blank = 10K, "E" = 100K). Both ratings are validated per MIL-STD-883 methods and apply across the full –55°C to +125°C operating range. The AT28HC256-70SU-T retains data for 10 years under those conditions.
AT28HC256-70SU-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 70 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28HC256-70SU-T FAQ
1.How can I place an order for AT28HC256-70SU-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256-70SU-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256-70SU-T reliable?
The price and inventory of AT28HC256-70SU-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256-70SU-T is usually 5 days.
3.What payment methods are accepted for AT28HC256-70SU-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256-70SU-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256-70SU-T?
AT28HC256-70SU-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256-70SU-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256-70SU-T?
For technical support, including AT28HC256-70SU-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256-70SU-T requirements.
6.How does Aetrix verify that AT28HC256-70SU-T is sourced from the original manufacturer or authorized distributors?
All AT28HC256-70SU-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256-70SU-T meets industry standards.
7.What is the process for return or replacement of AT28HC256-70SU-T?
All AT28HC256-70SU-T units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256-70SU-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256-70SU-T part is unused and in its original packaging.
Return procedure for AT28HC256-70SU-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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