Microchip Technology AT28HC256-90FM/883
- Part No.:
- AT28HC256-90FM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-CFlatPack
- Datasheet:
-
AT28HC256-90FM/883.pdf
- Description:
- IC EEPROM 256KBIT PAR 28FLATPK
- Quantity:
- Payment:

- Shipping:

Inventory:4,335
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256-90FM/883 from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 90 ns read access time, 10 ms maximum page write cycle time, and full operation across –55°C to +125°C. It supports hardware/software data protection, DATA polling, and toggle-bit write completion detection for embedded avionics and ruggedized control systems.
For engineers reviewing the AT28HC256-90FM/883 datasheet, AT28HC256-90FM/883 pinout, AT28HC256-90FM/883 application, or AT28HC256-90FM/883 equivalent, this device delivers deterministic timing, JEDEC-compliant byte-wide interface, and MIL-STD-883 qualified reliability in CERDIP and CLCC packages - critical for high-integrity memory retention in defense and aerospace platforms.
Technical Context
The AT28HC256-90FM/883 implements a paged architecture with an internal 64-byte latch, enabling simultaneous write of 1–64 bytes within a single page defined by address bits A6–A14. Its dual-line chip enable (CE) and output enable (OE) control allows precise bus contention management in multi-master systems.
It uses CMOS-compatible TTL-level I/O, operates from a single 5V ±10% supply, and integrates VCC sense, power-on delay, noise filtering, and software data protection (SDP) to prevent inadvertent writes during power transitions or EMI events.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32,768 × 8), organized as 64-byte pages - enables burst-write efficiency without external buffering |
| Read Access Time | 90 ns max - meets real-time response requirements in MIL-STD-1553 or discrete I/O controller interfaces |
| Page Write Cycle Time | 10 ms max - defines worst-case firmware update latency for field-programmable configuration storage |
| Operating Temperature | –55°C to +125°C - qualified per MIL-STD-883 Method 5005 - suitable for engine bay or space-grade electronics |
| Endurance & Retention | 10,000 write cycles / 10 years data retention - validated under military thermal cycling and bias stress conditions |
| Supply Current | 80 mA active / 3 mA CMOS standby - enables low-quiescent-power operation in always-on mission-critical subsystems |
| Interface Compatibility | JEDEC-approved byte-wide pinout, TTL/CMOS I/O - ensures drop-in replacement for legacy SRAM-based boot memory designs |
Pinout & Package
AT28HC256-90FM/883 is supplied in 32-lead CERDIP and 32-lead CLCC packages compliant with MIL-STD-1835 D-10 and C-12 configurations. Both packages feature hermetic ceramic sealing and gold-plated leads for long-term reliability in high-humidity or radiation-prone environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | Byte-wide parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit status indication |
| CE | Chip Enable | Active-low primary selection signal; must be stable before address setup to avoid spurious writes |
| OE | Output Enable | Active-low read control; enables high-impedance output when deasserted - prevents bus contention |
| WE | Write Enable | Active-low write strobe; falling edge latches data; combined with CE determines write mode (byte/page) |
| VCC | Power Supply | +5V ±10% supply; internal VCC sense disables writes below ~3.8V - prevents corruption during brownout |
| GND | Ground Reference | Signal and power ground reference; requires low-inductance connection to minimize switching noise on I/O lines |
| NC / DC | No Connect / Don't Connect | Pins marked NC or DC (e.g., pins 1 & 17 in CLCC) are unconnected - must remain floating per MIL-STD-883 |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Write Protection | VCC sense + 5 ms power-on delay + noise filter (15 ns pulse rejection) - eliminates need for external reset supervisors |
| Software Data Protection (SDP) | Three-byte unlock sequence (AAh/55h/A0h) required before any write - prevents accidental overwrites in flight software |
| DATA Polling & Toggle Bit | I/O7 complement feedback and I/O6 toggling provide deterministic, bus-compatible write completion signaling - no external timers needed |
| Page Write Architecture | Internal 64-byte latch frees address/data bus after first byte - enables concurrent CPU operations during 10 ms programming window |
| MIL-STD-883 Qualification | Tested per Method 5005 (temperature cycling), 5007 (hermeticity), and 5012 (radiation hardness assurance) - traceable to QML-V listing |
Applications
| Avionics Configuration Storage | Tactical Radio Firmware Bootloader |
|---|---|
|
Use Scenario: Storing aircraft-specific calibration tables, sensor compensation coefficients, and flight control law parameters in a fly-by-wire system. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed at power-up and during in-flight reconfiguration; 90 ns read time ensures deterministic boot latency. Use Value: Hermetic CERDIP package and –55°C to +125°C operation guarantee data integrity across stratospheric temperature excursions and vibration profiles. |
Use Scenario: Holding encrypted bootloader code and secure key material in a Type 1 COMSEC-certified handheld radio. IC Role / Device Role / Timing Role: Secure, tamper-resistant program memory with SDP-enabled write lock - prevents unauthorized firmware modification during field deployment. Use Value: 10,000-cycle endurance and 10-year retention meet NSA's INFOSEC lifecycle requirements for cryptographic key storage. |
| Missile Guidance System EEPROM | Spacecraft Onboard Telemetry Logger |
|
Use Scenario: Recording pre-launch alignment data, gyroscope bias offsets, and mission-specific trajectory parameters in solid-fuel missile guidance units. IC Role / Device Role / Timing Role: Radiation-tolerant nonvolatile memory with page-write capability - enables rapid field updates of mission-critical parameters prior to launch. Use Value: MIL-STD-883 qualification and 32-lead CLCC package ensure survivability under 20,000 g shock and vacuum outgassing constraints. |
Use Scenario: Capturing housekeeping telemetry (voltage, temperature, attitude) during orbital insertion and commissioning phases of a CubeSat platform. IC Role / Device Role / Timing Role: Low-power, high-reliability data logger memory; 3 mA standby current extends battery life during dormant orbital phases. Use Value: Single 5V supply simplifies power architecture; DATA polling eliminates need for watchdog timers in resource-constrained flight software. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-90DM/883 | Same die, but 28-pin CERDIP package (vs. 32-pin); lacks A13/A14 pins - limited to 128K address space | Used where board layout restricts to 28-pin footprint and 128K memory suffices | Select only if design does not require full 256K addressing or page-write flexibility beyond 32-byte pages |
| DS2502-E48+T&R | 1-Wire serial EEPROM (48-bit laser-programmed ID + 1Kbit user memory); no parallel interface or page write | Deployed in asset tracking, calibration certificate storage, and simple parameter backup - not for high-speed read/write | Choose for ultra-low pin count, parasitic power, or device-unique ID needs - not as functional replacement |
Compared with AT28HC256-90FM/883, AT28C256-90DM/883 offers identical timing and protection features but reduced density and pin count, while DS2502-E48+T&R trades parallel speed and page write for serial simplicity and built-in unique ID - neither provides full functional or pin-for-pin equivalence.
Availability
AT28HC256-90FM/883 is available at Aetrix Electronics and suitable for avionics, tactical communications, missile guidance, and spacecraft telemetry applications requiring stable component supply, long-term obsolescence mitigation, and MIL-STD-883 traceability.
Supply support for AT28HC256-90FM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions for industrial, automotive, and defense markets.
The AT28HC256 product line was developed to deliver radiation-hardened, temperature-qualified parallel EEPROMs for mission-critical systems where data integrity, deterministic timing, and long-term reliability supersede cost or density considerations.
FAQ
What is the maximum operating temperature range for the AT28HC256-90FM/883?
The AT28HC256-90FM/883 is fully specified and tested from –55°C to +125°C per MIL-STD-883 Method 5005. This extended range is achieved through hermetic packaging (CERDIP or CLCC), high-reliability metallization, and process-controlled CMOS fabrication - making it suitable for engine-mounted controllers and space-qualified electronics where ambient extremes exceed commercial limits. The AT28HC256-90FM/883 maintains full read/write functionality and timing compliance across this entire range.
Does the AT28HC256-90FM/883 support true page write, and what is the maximum page size?
Yes, the AT28HC256-90FM/883 supports true hardware-accelerated page write with a fixed 64-byte page size. The device latches up to 64 bytes internally using its dedicated page register, then executes the full write autonomously using an internal timer - freeing the address and data bus after the first byte. Each byte must be loaded within 150 µs of the prior one (tBLC), and all addresses must reside on the same page (defined by A6–A14). This capability is confirmed in the AT28HC256-90FM/883 datasheet Section 6.8 and Table 6-4.
How is write completion detected on the AT28HC256-90FM/883?
The AT28HC256-90FM/883 provides two hardware-supported methods: DATA polling on I/O7 (complement of last written byte appears until write completes) and toggle-bit detection on I/O6 (bit toggles continuously during write, then stabilizes). Both methods operate without external clocks or timers and are valid at any point during the write cycle. These mechanisms are electrically characterized and guaranteed across the full military temperature range - a key differentiator from software-polling-only alternatives. The AT28HC256-90FM/883 specification explicitly defines tWR and toggle timing in Tables 6-5 and 6-6.
What package types are available for the AT28HC256-90FM/883?
The AT28HC256-90FM/883 is manufactured exclusively in hermetically sealed, MIL-STD-1835-qualified packages: 32-lead CERDIP (MIL-STD-1835 D-10 Config A) and 32-lead CLCC (MIL-STD-1835 C-12). The "F" in the suffix denotes Philippines assembly, and "M/883" confirms full MIL-STD-883 testing. Unlike commercial variants, the AT28HC256-90FM/883 is not offered in flatpack or PGA packages - those are assigned different suffixes (e.g., ZA, UA) and distinct qualification records.
Is software data protection (SDP) enabled by default on the AT28HC256-90FM/883?
No, the AT28HC256-90FM/883 ships with software data protection disabled. SDP must be explicitly enabled via the three-byte unlock sequence (AAh to 5555h, 55h to 2AAAh, A0h to 5555h) - after which all subsequent writes require repeating the sequence. Once enabled, SDP persists through power cycles and protects against accidental writes during power-up/down transients. This behavior is documented in Section 6.11 of the AT28HC256-90FM/883 datasheet and verified in production test flow per MIL-STD-883 Method 5004.
AT28HC256-90FM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-CFlatPack
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-FlatPack, Ceramic Bottom-Brazed
AT28HC256-90FM/883 FAQ
1.How can I place an order for AT28HC256-90FM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256-90FM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256-90FM/883 reliable?
The price and inventory of AT28HC256-90FM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256-90FM/883 is usually 5 days.
3.What payment methods are accepted for AT28HC256-90FM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256-90FM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256-90FM/883?
AT28HC256-90FM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256-90FM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256-90FM/883?
For technical support, including AT28HC256-90FM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256-90FM/883 requirements.
6.How does Aetrix verify that AT28HC256-90FM/883 is sourced from the original manufacturer or authorized distributors?
All AT28HC256-90FM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256-90FM/883 meets industry standards.
7.What is the process for return or replacement of AT28HC256-90FM/883?
All AT28HC256-90FM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256-90FM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256-90FM/883 part is unused and in its original packaging.
Return procedure for AT28HC256-90FM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256-90FM/883 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

