My Inquiry
My Account
Microchip Technology AT28HC256-90JI
- Part No.:
- AT28HC256-90JI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28HC256-90JI.pdf
- Description:
- IC EEPROM 256KBIT PAR 32PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:4,753
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256-90JI from Microchip Technology (formerly Atmel) is a 256 Kbit (32K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 90 ns read access time, 3–10 ms page write cycle, and industrial temperature range (−40°C to +85°C). It operates from a single 5V ±10% supply, supports hardware/software data protection, and is used in embedded control firmware storage, industrial PLC configuration memory, and legacy system BIOS backup.
For engineers reviewing the AT28HC256-90JI datasheet, AT28HC256-90JI pinout, AT28HC256-90JI application, or AT28HC256-90JI equivalent, key selection criteria include verified 90 ns read timing, 64-byte page write capability with DATA Polling/Toggle Bit write completion detection, industrial-grade reliability (10⁴/10⁵ endurance cycles, 10-year data retention), and compatibility with TTL/CMOS bus interfaces without external logic.
Technical Context
The AT28HC256-90JI implements a CMOS-based parallel EEPROM architecture with internal address/data latching for up to 64-byte page writes and an autonomous internal control timer. Its dual-line chip enable (CE) and output enable (OE) logic enables flexible bus contention management in shared-memory systems.
Write operations support both byte and page modes, with software data protection (SDP) enabled via a three-byte command sequence at addresses 5555H/2AAAH/5555H. End-of-write detection is implemented via I/O7 DATA Polling or I/O6 Toggle Bit, eliminating need for fixed delay timers in host firmware.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32,768 × 8), organized as byte-addressable parallel array |
| Read Access Time | 90 ns maximum - ensures compatibility with 10 MHz bus timing in legacy microcontroller systems |
| Page Write Cycle | 3 ms (F-option) or 10 ms (standard) - reduces firmware update latency vs. byte-by-byte writes |
| Endurance | 10,000 or 100,000 write cycles - validated for repeated field-upgrade applications |
| Data Retention | 10 years at +85°C - guarantees long-term configuration integrity in unattended industrial equipment |
| Supply Voltage | 5 V ±10% - interoperable with standard TTL/CMOS logic families without level-shifting |
| Operating Temperature | −40°C to +85°C - qualified for industrial control cabinets and outdoor telemetry units |
Pinout & Package
AT28HC256-90JI is supplied in a 28-lead plastic J-leaded chip carrier (PLCC, package code 32J) with JEDEC-standard byte-wide pinout. Pin 1 is marked by corner notch; pins 1 and 17 are No Connect (NC).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bi-directional Data Bus | CMOS/TTL-compatible 8-bit data path; supports true read/write without external transceivers |
| CE | Chip Enable | Active-low device select; must be low with OE low and WE high for valid read access |
| OE | Output Enable | Active-low output control; enables high-impedance state when high to prevent bus contention |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; rising edge initiates internal programming |
| VCC, GND | Power Supply | Single 5V supply with <3 mA standby current - suitable for low-power wake-on-event designs |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte Page Write | Reduces firmware update time by up to 64× vs. sequential byte writes; eliminates host-side address incrementing overhead |
| DATA Polling (I/O7) | Enables real-time write completion detection without fixed delays - improves system responsiveness and deterministic timing |
| Software Data Protection (SDP) | Prevents accidental writes during power transitions via user-configurable 3-byte unlock sequence - critical for field-deployed devices |
| VCC Sense & Power-on Delay | Hardware write inhibit below 3.8 V and 5 ms post-power-up lockout - eliminates corruption during brown-out conditions |
| JEDEC Byte-wide Pinout | Direct drop-in replacement for industry-standard 27C256/27C512 EPROMs in existing PCB layouts - no redesign required |
Applications
| Industrial PLC Configuration Storage | Legacy System BIOS Backup |
|---|---|
Use Scenario: Storing ladder logic programs and I/O mapping tables in programmable logic controllers operating in factory-floor environments with wide temperature swings and EMI. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via parallel bus during boot and runtime parameter updates. Use Value: 10-year data retention and −40°C to +85°C operation ensure reliable parameter persistence across maintenance cycles without battery backup. | Use Scenario: Preserving BIOS settings and boot firmware in x86-based industrial PCs and embedded motherboards where flash upgrade paths are constrained. IC Role / Device Role / Timing Role: Parallel EEPROM providing direct CPU bus access for fast read during POST and protected write during setup utility execution. Use Value: 90 ns read timing meets legacy chipset timing budgets; SDP prevents inadvertent corruption during unexpected power loss. |
| Embedded Controller Firmware Storage | Medical Device Calibration Data |
Use Scenario: Holding application firmware images in microcontroller-based motor drives and HVAC controllers requiring field-upgradable code. IC Role / Device Role / Timing Role: External program memory mapped into MCU address space; supports in-system reprogramming via page writes. Use Value: 3 ms page write (F-option variant) cuts firmware update time by >95% vs. byte writes - critical for minimizing machine downtime. | Use Scenario: Storing sensor calibration coefficients and usage logs in Class II medical instruments subject to strict traceability and data integrity requirements. IC Role / Device Role / Timing Role: Secure nonvolatile memory with hardware VCC-sense and software lockout protecting against unintended overwrites. Use Value: 100K-cycle endurance option (AT28HC256E) supports lifetime recalibration; 10-year retention satisfies FDA 21 CFR Part 11 record-keeping mandates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-90JI | Same pinout and timing, but lacks software data protection (SDP) and internal error correction; 10K endurance only | Suitable for cost-sensitive, non-critical firmware storage where write protection is handled externally | Select if SDP and extended endurance are not required; verify external write-lock circuitry exists |
| MX28LV256AL-90JN | 3.3 V core with 5 V tolerant I/O; 90 ns read; 5 ms page write; no SDP; different pinout (SOIC-28) | Requires level translation in 5 V systems; suited for newer low-voltage designs with footprint flexibility | Choose only if migrating to 3.3 V architecture; not pin-compatible - PCB redesign needed |
Compared with AT28HC256-90JI, AT28C256-90JI offers identical timing and packaging but omits SDP and advanced reliability features, while MX28LV256AL-90JN shifts to 3.3 V operation and requires layout changes - making AT28HC256-90JI the optimal choice for industrial 5 V systems needing robust, drop-in firmware storage.
Availability
AT28HC256-90JI is available at Aetrix Electronics and suitable for industrial PLC configuration storage, legacy system BIOS backup, and embedded controller firmware storage requiring stable component supply across extended product lifecycles.
Supply support for AT28HC256-90JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for the AT28HC256 family, including datasheets, application notes, and long-term supply commitments for industrial and military-grade variants.
The AT28HC256 product line was designed for high-reliability, pin-compatible replacement of UV-erasable EPROMs in legacy 5 V embedded systems - emphasizing robustness, ease of integration, and backward compatibility.
FAQ
What is the guaranteed read access time for AT28HC256-90JI?
The AT28HC256-90JI guarantees a maximum read access time of 90 ns under industrial temperature conditions (−40°C to +85°C) and 5 V ±10% supply. This specification is fully characterized and tested per AC Read Characteristics Table on page 6 of the official datasheet, ensuring timing compliance in 10 MHz bus systems without wait states.
Does AT28HC256-90JI support page write operations, and what is the maximum page size?
Yes, AT28HC256-90JI supports page write operations with a maximum size of 64 bytes. The device uses internal latches to store address and data during the write cycle, allowing the host bus to be released immediately after initiating the write. Page boundaries are defined by address bits A6–A14, and all bytes within a page must be written within 150 µs of each other.
How does software data protection (SDP) work on AT28HC256-90JI?
AT28HC256-90JI implements software data protection via a three-byte unlock sequence written to addresses 5555H, 2AAAH, and 5555H. Once enabled, all subsequent writes require repeating this sequence before data. SDP remains active across power cycles and is disabled only by a separate five-byte disable command. The feature is shipped disabled from factory.
What package type is used for AT28HC256-90JI, and is it JEDEC-compliant?
AT28HC256-90JI uses a 32-lead plastic J-leaded chip carrier (PLCC, package code 32J) conforming to JEDEC MS-016, Variation AE. It features a standard byte-wide pinout identical to industry-standard EPROMs like 27C256, enabling direct PCB replacement without layout modification.
Can AT28HC256-90JI be used in place of older 27C256 EPROMs?
Yes, AT28HC256-90JI is designed as a functional and pin-compatible EEPROM replacement for 27C256 EPROMs. It matches the 28-pin DIP/PLCC footprints and JEDEC byte-wide pinout, operates from the same 5 V supply, and supports identical read timing - eliminating need for PCB changes while adding in-system reprogrammability and no UV erasure requirement.
AT28HC256-90JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28HC256-90JI FAQ
1.How can I place an order for AT28HC256-90JI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256-90JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256-90JI reliable?
The price and inventory of AT28HC256-90JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256-90JI is usually 5 days.
3.What payment methods are accepted for AT28HC256-90JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256-90JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256-90JI?
AT28HC256-90JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256-90JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256-90JI?
For technical support, including AT28HC256-90JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256-90JI requirements.
6.How does Aetrix verify that AT28HC256-90JI is sourced from the original manufacturer or authorized distributors?
All AT28HC256-90JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256-90JI meets industry standards.
7.What is the process for return or replacement of AT28HC256-90JI?
All AT28HC256-90JI units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256-90JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256-90JI part is unused and in its original packaging.
Return procedure for AT28HC256-90JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256-90JI Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
