My Inquiry
My Account
Microchip Technology AT28HC256-90JU
- Part No.:
- AT28HC256-90JU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28HC256-90JU.pdf
- Description:
- IC EEPROM 256KBIT PAR 32PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:2,800
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256-90JU from Microchip Technology is a 256-Kbit (32,768 × 8) parallel EEPROM with 90 ns read access time, single 5V ±10% supply, JEDEC-standard byte-wide pinout, and industrial temperature range (–40°C to +85°C). It supports automatic 1–64-byte page writes with internal latching and data polling for write completion detection, used in embedded system configuration storage and firmware parameter retention.
For engineers reviewing the AT28HC256-90JU datasheet, AT28HC256-90JU pinout, AT28HC256-90JU application, or AT28HC256-90JU equivalent, key selection criteria include its 90 ns read timing, 3 mA standby current, hardware/software write protection, 10,000-cycle endurance, and PLCC-32 packaging compatibility with legacy 8-bit microcontroller buses.
Technical Context
The AT28HC256-90JU implements a static RAM-compatible parallel interface with dual-line chip enable (CE) and output enable (OE) control, enabling bus contention avoidance in multi-device systems. Its internal 64-byte page register allows burst loading of up to 64 bytes before initiating an autonomous internal write cycle timed by an on-chip control timer.
Write completion is signaled via DATA Polling (I/O7 complement toggle) or Toggle Bit (I/O6 state alternation), both operable at any point during tWC. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs, while software data protection uses a three-byte command sequence to enable/disable write lock.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32,768 × 8) - supports full 16-bit address space with byte-level random access |
| Read Access Time | 90 ns - meets timing requirements for 11 MHz Z80, 8051, and 68K-based systems |
| Page Write Cycle | ≤10 ms - enables efficient bulk updates without external timing circuitry |
| Endurance | 10,000 write/erase cycles - sufficient for field-updatable calibration tables and logging buffers |
| Standby Current | 3 mA - reduces power in sleep-mode industrial controllers |
| Data Retention | 10 years - ensures long-term reliability in unpowered storage applications |
| Supply Voltage | 5V ±10% - compatible with standard TTL/CMOS logic rails without regulation |
| Operating Temp | –40°C to +85°C - qualified for industrial automation and automotive under-hood ECUs |
Pinout & Package
AT28HC256-90JU is supplied in a 32-lead Plastic Leaded Chip Carrier (PLCC) package with gull-wing leads, RoHS-compliant green molding compound, and JEDEC-standard footprint. Pin 1 is marked by a corner chamfer; pins 1 and 17 are "Don't Connect" (DC) and must remain unconnected per datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus (A0 LSB to A14 MSB) selects one of 32,768 bytes; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path; I/O7 provides DATA Polling feedback, I/O6 provides Toggle Bit status |
| CE | Chip Enable | Active-low device select; must be low for read/write; high-Z output when asserted high |
| OE | Output Enable | Active-low output gate; controls data bus drive; enables bus sharing with other peripherals |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; initiates byte or page programming |
| VCC | Power Supply | +5V ±10% main supply; powers core logic and memory array |
| GND | Ground Reference | Signal and power return; requires low-impedance connection to minimize noise coupling |
| NC / DC | No Connect / Don't Connect | Pins 1 and 17 are internally unconnected; must be left floating or tied to GND per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-Wide Pinout | Direct drop-in replacement for industry-standard 27C256 and 28C256 EPROMs/EEPROMs without PCB redesign |
| Automatic Page Write | Reduces host CPU overhead by accepting up to 64 bytes in rapid succession before internal programming begins |
| DATA Polling & Toggle Bit | Eliminates need for fixed delay timers or external busy signals during write operations |
| Hardware + Software Write Protection | Prevents corruption during power ramp-up/down and accidental firmware overwrites via configurable lock |
| 64-Byte Device ID Area | Enables unique serialization, calibration offset storage, or traceability data using A9 = 12V programming mode |
| CMOS/TTL Compatibility | Interoperates with both 5V CMOS and bipolar logic families without level-shifting components |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Tables |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory environments. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during boot and runtime via parallel bus; 90 ns read speed supports real-time scan cycle execution. Use Value: Ensures deterministic startup behavior and retains settings across power loss without battery backup. | Use Scenario: Holding sensor-specific calibration coefficients and safety-critical operational limits in portable diagnostic equipment. IC Role / Device Role / Timing Role: Parameter EEPROM interfaced to microcontroller's external memory bus; software data protection prevents unauthorized modification of medical settings. Use Value: Meets IEC 62304 software lifecycle requirements for persistent data integrity and traceability. |
| Automotive Body Control Module (BCM) | Legacy Industrial HMI Firmware Patch Storage |
Use Scenario: Storing seat/mirror position presets, lighting profiles, and door lock configurations in 12V automotive BCMs operating at –40°C to +85°C. IC Role / Device Role / Timing Role: Parallel EEPROM connected to 8-bit MCU bus; hardware VCC-sense protection prevents writes during cold cranking voltage sag. Use Value: Guarantees reliable operation across automotive battery transients and extended temperature exposure. | Use Scenario: Hosting field-upgradable firmware patches for aging CNC machine controllers using existing 28-pin socketed footprint. IC Role / Device Role / Timing Role: Drop-in replacement for obsolete 27C256 EPROMs; page write capability accelerates patch deployment vs. byte-by-byte programming. Use Value: Extends service life of legacy equipment without redesigning PCBs or changing drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC256-90PU | Same die, 28-lead SOIC package; no DC pins; smaller footprint but lower thermal mass | Suitable for space-constrained designs where PLCC rework is impractical | Select when board area is critical and thermal cycling stress is minimal |
| ST M28W256F | 256 Kbit parallel EEPROM with 100 ns access, 5V-only, 32-lead PLCC, but lacks software data protection | Requires external hardware write-enable logic for secure updates | Choose only if software lock is unnecessary and longer access time is acceptable |
Compared with AT28HC256-90PU, the AT28HC256-90JU offers superior thermal dissipation and mechanical robustness in high-vibration environments; versus ST M28W256F, it delivers integrated security features essential for certified medical and industrial firmware storage.
Availability
AT28HC256-90JU is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, automotive body control modules, and legacy HMI firmware updates requiring stable component supply and long-term obsolescence management.
Supply support for AT28HC256-90JU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global provider of microcontrollers, analog devices, and nonvolatile memory solutions, serving industrial, automotive, and consumer markets with ISO 9001-certified manufacturing.
The AT28HC256 belongs to Microchip's industrial-grade parallel EEPROM product line, designed specifically for reliable, pin-compatible replacement of legacy EPROMs in 5V embedded systems requiring field-updatable nonvolatile storage.
FAQ
What is the maximum page write size supported by the AT28HC256-90JU?
The AT28HC256-90JU supports up to 64 bytes per page write operation. This is enabled by its internal 64-byte page register, which latches address and data upon the first write strobe. Subsequent bytes must be loaded within 150 µs of the prior byte (tBLC), and all addresses must reside on the same page defined by A6–A14. The AT28HC256-90JU completes the internal programming autonomously after the final byte is accepted.
Does the AT28HC256-90JU require external high-voltage programming circuitry?
No, the AT28HC256-90JU operates from a single 5V ±10% supply and does not require external high-voltage programming. The only exception is the optional 12V ±0.5V pulse on A9 for accessing the 64-byte device identification area - this is strictly for serialization and not required for normal read/write operations. All standard byte and page writes use only VCC.
How does hardware write protection function on the AT28HC256-90JU?
Hardware write protection on the AT28HC256-90JU activates automatically when VCC drops below ~3.8 V, preventing writes during brown-out conditions. It also enforces a 5 ms power-on delay after VCC reaches threshold and filters noise pulses shorter than 15 ns on WE/CE lines. Additionally, write cycles are inhibited if OE is low, CE is high, or WE is high - ensuring safe default states during reset or bus contention.
Can the AT28HC256-90JU be used as a direct replacement for the AT27C256 EPROM?
Yes, the AT28HC256-90JU is pin-compatible and functionally equivalent to the AT27C256 EPROM in read mode, with identical JEDEC byte-wide pinout and 32,768 × 8 organization. Unlike the EPROM, it requires no UV erasure and supports in-system electrical reprogramming. However, write timing and control logic differ: the AT28HC256-90JU uses WE/CE/OE handshaking instead of OE-only reads, and its write cycles are self-timed.
What is the purpose of the "DC" pins on the AT28HC256-90JU PLCC package?
The "DC" (Don't Connect) pins on the AT28HC256-90JU - pins 1 and 17 in the 32-lead PLCC package - are internally unconnected and must remain floating or tied to GND per Microchip's layout recommendations. They serve no electrical function and are retained for mechanical symmetry and package standardization. Connecting them to VCC or signal lines may cause undefined behavior or damage.
AT28HC256-90JU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28HC256-90JU FAQ
1.How can I place an order for AT28HC256-90JU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256-90JU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256-90JU reliable?
The price and inventory of AT28HC256-90JU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256-90JU is usually 5 days.
3.What payment methods are accepted for AT28HC256-90JU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256-90JU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256-90JU?
AT28HC256-90JU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256-90JU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256-90JU?
For technical support, including AT28HC256-90JU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256-90JU requirements.
6.How does Aetrix verify that AT28HC256-90JU is sourced from the original manufacturer or authorized distributors?
All AT28HC256-90JU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256-90JU meets industry standards.
7.What is the process for return or replacement of AT28HC256-90JU?
All AT28HC256-90JU units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256-90JU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256-90JU part is unused and in its original packaging.
Return procedure for AT28HC256-90JU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256-90JU Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
