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Microchip Technology AT28HC256-90LM/883
- Part No.:
- AT28HC256-90LM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-CLCC
- Datasheet:
-
AT28HC256-90LM/883.pdf
- Description:
- IC EEPROM 256KBIT PARALLEL 32LCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,099
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Product details
Overview
AT28HC256-90LM/883 from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 90 ns read access time, 10 ms maximum page write cycle time, and full operation across −55°C to +125°C. It features hardware/software data protection, DATA polling and toggle-bit write completion detection, and JEDEC-standard byte-wide pinout for integration into avionics, missile guidance, and hardened embedded control systems.
For engineers reviewing the AT28HC256-90LM/883 datasheet, AT28HC256-90LM/883 pinout, AT28HC256-90LM/883 application, or AT28HC256-90LM/883 equivalent, this page delivers verified military-spec timing, endurance (10,000 cycles), power behavior (3 mA CMOS standby), package mapping (32-lead CLCC), and real-world substitution guidance - all extracted from Microchip DS20006352A and MIL-PRF-38535 qualified documentation.
Technical Context
The AT28HC256-90LM/883 implements a paged architecture with an internal 64-byte latch enabling simultaneous writes of 1–64 bytes per cycle. Its dual-line chip enable (CE) and output enable (OE) control logic supports bus contention avoidance in multi-master systems, while VCC sense and 5 ms power-on delay circuitry prevent inadvertent writes during supply ramp-up.
Write completion is confirmed via I/O7 DATA polling (complement-to-data response) or I/O6 toggle-bit monitoring - both usable at any point during tWC. The device includes 64 bytes of dedicated identification memory accessible at 7FC0H–7FFFH using A9 = 12V, and optional software chip erase via a 6-byte command sequence.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 256 Kbit (32,768 × 8), organized as byte-addressable nonvolatile storage |
| Read access time | 90 ns max - enables direct replacement of SRAM in legacy MIL-STD-1553 or TMS320C3x-based systems without wait-state insertion |
| Page write time | 10 ms max - supports burst configuration updates in flight computers where latency must be bounded |
| Endurance | 10,000 write/erase cycles - validated under MIL-PRF-38535 Class B screening for mission-critical reprogramming |
| Data retention | 10 years at +125°C - meets long-term storage requirements for deployed munitions and satellite subsystems |
| Supply voltage | 5 V ±10% - compatible with standard military power buses without regulation overhead |
| Operating temperature | −55°C to +125°C - qualified per MIL-STD-883 Method 1010 for hermetic ceramic packages |
| Standby current | 3 mA (CMOS), 300 µA (ISB2) - enables low-power dormant mode in battery-backed telemetry recorders |
Pinout & Package
AT28HC256-90LM/883 is supplied in a 32-lead Ceramic Leadless Chip Carrier (CLCC), compliant with MIL-STD-1835 C-12. Pin 1 is indexed at top-left corner; pins 1 and 17 are "Don't Connect" (DC) per Microchip DS20006352A-page 4.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional data bus | CMOS/TTL-compatible 8-bit parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit status |
| CE | Chip Enable | Active-low device select; must be low with OE low and WE high for read access |
| OE | Output Enable | Active-low output gate; controls tri-state buffer - critical for shared-bus arbitration |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; noise-filtered against <15 ns glitches |
| VCC | Power supply | 5 V ±10% input; internal VCC sense disables writes below 3.8 V typical |
| GND | Ground reference | Signal and power return; decoupling required per MIL-STD-1537 for EMI resilience |
| DC (pins 1, 17) | No-connect | Unbonded terminals - must remain unconnected per Microchip package marking spec |
Key Features
| Feature | Design Value |
|---|---|
| Hardware data protection | VCC sense + 5 ms power-on delay + noise filtering on CE/WE - eliminates need for external POR circuitry in launch vehicle sequencers |
| Software data protection (SDP) | Three-step AA/55/A0 unlock sequence - allows selective firmware update zones in airborne navigation modules |
| Page write capability | 64-byte internal latch with 150 µs byte-load cycle (tBLC) - enables atomic parameter block writes in radar calibration tables |
| Identification memory | 64 bytes at 7FC0H–7FFFH, accessed with A9 = 12 V - stores unit serial, calibration date, and burn-in lot traceability |
| Toggle-bit write detection | I/O6 toggles until tWC completes - provides asynchronous status without consuming I/O7 or requiring address reissue |
Applications
| Avionics Data Logging | Missile Guidance Memory |
|---|---|
Use Scenario: Continuous recording of inertial measurement unit (IMU) outputs and GPS timestamps during powered flight phases. IC Role / Device Role / Timing Role: Nonvolatile storage buffer interfaced directly to MIL-STD-1553B RT with 90 ns read timing synchronized to 10 kHz sample clock. Use Value: Eliminates external SRAM + battery backup; 10-year data retention ensures post-mission forensic analysis of flight dynamics. | Use Scenario: Storing target acquisition profiles, seeker calibration coefficients, and pre-launch mission parameters in solid-fuel tactical missiles. IC Role / Device Role / Timing Role: Configuration memory mapped into DSP address space; page writes update seeker gain tables during ground checkout. Use Value: 10,000-cycle endurance supports repeated field reprogramming; −55°C to +125°C operation survives motor ignition thermal shock. |
| Secure Crypto Key Storage | Hardened Industrial PLC |
Use Scenario: Holding AES-256 keys and certificate fingerprints in tamper-resistant communication modules for SATCOM terminals. IC Role / Device Role / Timing Role: Isolated memory partition accessed only after SDP unlock sequence; 12 V A9 programming enables secure key injection during factory provisioning. Use Value: Hardware+software protection prevents glitch-based key extraction; 64-byte ID area stores cryptographic binding tokens. | Use Scenario: Retaining ladder logic state, I/O mapping, and fault history in nuclear plant safety controllers exposed to gamma radiation. IC Role / Device Role / Timing Role: Nonvolatile shadow RAM for redundant CPU pairs; CE/OE dual-control prevents bus conflicts during failover transitions. Use Value: Hermetic CLCC package resists moisture ingress; 3 mA standby current extends UPS runtime during station blackouts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC256-12LM/883 | 120 ns read access time; same 10 ms page write, endurance, and temperature range | Suitable where system timing budget allows longer tACC; identical pinout and software compatibility | Select when 90 ns timing margin is unnecessary and cost optimization is prioritized |
| DS2502-E48+T&R | 1-Wire serial interface; 1024-bit EPROM (not EEPROM); no write cycling endurance rating | Used for simple device ID tagging; lacks page write, DATA polling, or military temp support | Only for passive identification - not a functional substitute for programmable configuration storage |
Compared with AT28HC256-12LM/883, the AT28HC256-90LM/883 delivers tighter read timing for high-speed bus interfaces; compared with DS2502-E48+T&R, it provides full reprogrammability, deterministic write latency, and MIL-SPEC environmental robustness - making it the sole qualified choice for active firmware/configuration storage in defense platforms.
Availability
AT28HC256-90LM/883 is available at Aetrix Electronics and suitable for avionics data logging, missile guidance memory, and secure crypto key storage requiring stable component supply under extended temperature and radiation-hardened conditions.
Supply support for AT28HC256-90LM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with ISO 9001-certified manufacturing and MIL-PRF-38535 qualification capabilities.
The AT28HC256 product line was designed specifically for high-reliability, military-temperature EEPROM applications requiring paged write efficiency, hardware/software write protection, and JEDEC-compliant parallel interfacing in defense and aerospace systems.
FAQ
What is the maximum operating temperature range for the AT28HC256-90LM/883?
The AT28HC256-90LM/883 is fully specified and tested over −55°C to +125°C, meeting MIL-STD-883 Method 1010 requirements for hermetic ceramic packages. This range is validated for continuous operation, not just storage, and applies to all electrical characteristics including 90 ns read access and 10 ms page write timing.
Does the AT28HC256-90LM/883 support page write operations, and what is the maximum page size?
Yes, the AT28HC256-90LM/883 supports page write operations with a maximum size of 64 bytes per cycle. The device uses an internal address and data latch to accept up to 63 additional bytes within 150 µs (tBLC) of the first byte, provided all addresses reside on the same page defined by A6–A14.
How is write completion detected on the AT28HC256-90LM/883?
Write completion on the AT28HC256-90LM/883 can be detected using either DATA polling (monitoring complement-to-data on I/O7) or the toggle-bit method (observing I/O6 toggling state). Both methods are usable at any time during the write cycle and do not require halting system operation.
What package type is used for the AT28HC256-90LM/883, and are there unused pins?
The AT28HC256-90LM/883 uses a 32-lead Ceramic Leadless Chip Carrier (CLCC) per MIL-STD-1835 C-12. Pins 1 and 17 are designated "Don't Connect" (DC) and must remain unconnected - they are unbonded per Microchip DS20006352A-page 4 and package marking spec.
Is software data protection (SDP) enabled by default on the AT28HC256-90LM/883?
No, software data protection (SDP) is disabled by default on the AT28HC256-90LM/883. It must be explicitly enabled using the three-step AA/55/A0 unlock sequence written to addresses 5555H, 2AAAH, and 5555H. Once enabled, SDP remains active through power cycles until the disable sequence (AA/55/80/AA/20) is issued.
AT28HC256-90LM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-CLCC
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-LCC (11.43x13.97)
AT28HC256-90LM/883 FAQ
1.How can I place an order for AT28HC256-90LM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256-90LM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256-90LM/883 reliable?
The price and inventory of AT28HC256-90LM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256-90LM/883 is usually 5 days.
3.What payment methods are accepted for AT28HC256-90LM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256-90LM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256-90LM/883?
AT28HC256-90LM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256-90LM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256-90LM/883?
For technical support, including AT28HC256-90LM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256-90LM/883 requirements.
6.How does Aetrix verify that AT28HC256-90LM/883 is sourced from the original manufacturer or authorized distributors?
All AT28HC256-90LM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256-90LM/883 meets industry standards.
7.What is the process for return or replacement of AT28HC256-90LM/883?
All AT28HC256-90LM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256-90LM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256-90LM/883 part is unused and in its original packaging.
Return procedure for AT28HC256-90LM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256-90LM/883 Tags
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