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Microchip Technology AT28HC256-90UM/883

Name: AT28HC256-90UM/883
Brand: Microchip Technology
SKU: AT28HC256-90UM/883
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AT28HC256-90UM/883

Manufacturer:: Microchip Technology

Category:: Memory

Package:: 28-BCPGA

Datasheet:: AT28HC256-90UM/883.pdf

Description:: IC EEPROM 256KBIT PAR 28CPGA

Quantity:: RFQ Add To RFQ list

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Product details

Overview

AT28HC256-90UM/883 from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 90 ns read access time, 10 ms maximum page write cycle time, and full operation across –55°C to +125°C. It features hardware/software data protection, DATA polling for write completion detection, and JEDEC-standard byte-wide pinout. It serves as nonvolatile program/data storage in avionics control units requiring high reliability and radiation-tolerant memory.

For engineers reviewing the AT28HC256-90UM/883 datasheet, AT28HC256-90UM/883 pinout, AT28HC256-90UM/883 application, or AT28HC256-90UM/883 equivalent, key selection criteria include military temperature compliance, 90 ns read timing, 32-pin PGA package compatibility, page-write endurance (10,000 cycles), and software data protection enable/disable sequences.

Technical Context

The AT28HC256-90UM/883 implements a paged architecture with an internal 64-byte latch enabling simultaneous write of 1–64 bytes per cycle. Its dual-line chip enable (CE) and output enable (OE) control supports bus contention avoidance in multi-master systems. Write operations are governed by internal timing logic with automatic termination after tWC (≤10 ms).

It integrates VCC sense circuitry that inhibits writes below 3.8 V, a 5 ms power-on delay before write enable, and noise filtering rejecting sub-15 ns pulses on WE/CE. Data polling uses I/O7 complement feedback, while toggle-bit verification relies on I/O6 state alternation during active programming.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Size	256 Kbit (32,768 × 8) - fixed byte-wide organization; no address multiplexing required.
Read Access Time	90 ns - guarantees deterministic read latency under military temperature range (–55°C to +125°C).
Page Write Cycle Time	≤10 ms - maximum duration for internal programming of up to 64 bytes; enables burst configuration updates.
Endurance	10,000 write/erase cycles - validated at full military temperature range; sufficient for field-programmable firmware patches.
Data Retention	10 years - minimum guaranteed data integrity without refresh, critical for long-deployment platforms.
Supply Voltage	5 V ±10% - single-rail operation compatible with legacy TTL/CMOS logic families.
Operating Temperature	–55°C to +125°C - meets MIL-STD-883 Class B requirements for harsh-environment electronics.

Pinout & Package

AT28HC256-90UM/883 is supplied in a 30-pin Ceramic Pin Grid Array (PGA) package compliant with MIL-STD-1835 U-configuration. Pin 1 is index-marked; pins 1–28 carry address, data, and control signals; pins 29 (VCC) and 30 (GND) are power terminals.

Pin/Terminal	Circuit Role	Design Meaning
A0–A14	Address Inputs	15-bit address bus supporting full 32,768-word addressing; A6–A14 define page boundaries for write operations.
I/O0–I/O7	Bidirectional Data Bus	Byte-wide parallel interface; I/O7 provides DATA polling feedback; I/O6 delivers toggle-bit status during writes.
CE	Chip Enable	Active-low device select; must be low with OE low and WE high for read access; initiates write when pulsed low with OE high.
OE	Output Enable	Active-low output gate; controls data bus drive; high during write cycles to prevent contention.
WE	Write Enable	Active-low write strobe; falling edge latches address and data; rising edge triggers internal write timer.
VCC	Power Supply	+5 V ±10% supply input; powers all internal logic and memory array; monitored for write inhibition below 3.8 V.
GND	Ground Reference	Signal and power return path; decoupling required within 10 mm of VCC pin per MIL-PRF-38535.

Key Features

Feature	Design Value
Hardware Data Protection	VCC sense, 5 ms power-on delay, and noise filtering prevent spurious writes during power transients or EMI events.
Software Data Protection (SDP)	Three-step command sequence (AAh/55h/A0h to 5555h/2AAAh/5555h) enables/disables write lock; persists through power cycles.
Page Write Architecture	64-byte internal latch allows sequential loading of up to 64 bytes within 150 µs intervals; reduces host CPU overhead vs. byte-by-byte writes.
Write Completion Detection	DATA polling (I/O7 complement) and toggle-bit (I/O6 alternation) provide two independent, real-time methods to confirm write completion.
Military Qualification	Qualified per MIL-STD-883 Method 5005 (temperature cycling), 5008 (steady-state life), and 5012 (radiation hardness assurance).

Applications

Avionics Flight Control Memory	Secure Bootloader Storage
Use Scenario: Stores flight control law parameters and sensor calibration coefficients in airborne mission computers operating at altitude and extreme thermal gradients. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via parallel bus during system initialization and runtime reconfiguration; 90 ns read ensures timely parameter fetch during control loop execution. Use Value: 10-year data retention and 10,000-cycle endurance support field updates without hardware replacement; military temperature rating eliminates derating concerns.	Use Scenario: Holds immutable bootloader code and cryptographic keys in secure embedded systems where firmware integrity is enforced by hardware root-of-trust. IC Role / Device Role / Timing Role: Read-only execution memory during boot phase; software data protection prevents unauthorized modification of boot vectors or signature checks. Use Value: Dual write-protection mechanisms (hardware VCC sense + SDP command lock) ensure bootloader immutability across power cycles and voltage sags.
Tactical Radio Firmware Storage	Spacecraft Telemetry Configuration
Use Scenario: Stores frequency-hopping tables, encryption keys, and channel profiles in manpack and vehicular radios deployed in desert and arctic environments. IC Role / Device Role / Timing Role: Field-upgradable firmware repository accessed over parallel bus; page write mode enables rapid profile switching during mission re-tasking. Use Value: 32-pin PGA package provides hermetic sealing and mechanical robustness; 10 ms max write time enables <100 ms profile reload during radio handover.	Use Scenario: Maintains telemetry scaling factors, sensor bias offsets, and health-monitoring thresholds in satellite onboard computers exposed to vacuum and total ionizing dose. IC Role / Device Role / Timing Role: Radiation-tolerant nonvolatile memory for critical housekeeping data; JEDEC pinout ensures compatibility with legacy space-qualified PCB layouts. Use Value: Qualified per MIL-STD-883 assures performance after 100 krad(Si) TID exposure; 10-year retention supports multi-year orbital missions without refresh.

Avionics Flight Control Memory

Secure Bootloader Storage

Use Scenario: Stores flight control law parameters and sensor calibration coefficients in airborne mission computers operating at altitude and extreme thermal gradients.

IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via parallel bus during system initialization and runtime reconfiguration; 90 ns read ensures timely parameter fetch during control loop execution.

Use Value: 10-year data retention and 10,000-cycle endurance support field updates without hardware replacement; military temperature rating eliminates derating concerns.

Use Scenario: Holds immutable bootloader code and cryptographic keys in secure embedded systems where firmware integrity is enforced by hardware root-of-trust.

IC Role / Device Role / Timing Role: Read-only execution memory during boot phase; software data protection prevents unauthorized modification of boot vectors or signature checks.

Use Value: Dual write-protection mechanisms (hardware VCC sense + SDP command lock) ensure bootloader immutability across power cycles and voltage sags.

Tactical Radio Firmware Storage

Spacecraft Telemetry Configuration

Use Scenario: Stores frequency-hopping tables, encryption keys, and channel profiles in manpack and vehicular radios deployed in desert and arctic environments.

IC Role / Device Role / Timing Role: Field-upgradable firmware repository accessed over parallel bus; page write mode enables rapid profile switching during mission re-tasking.

Use Value: 32-pin PGA package provides hermetic sealing and mechanical robustness; 10 ms max write time enables <100 ms profile reload during radio handover.

Use Scenario: Maintains telemetry scaling factors, sensor bias offsets, and health-monitoring thresholds in satellite onboard computers exposed to vacuum and total ionizing dose.

IC Role / Device Role / Timing Role: Radiation-tolerant nonvolatile memory for critical housekeeping data; JEDEC pinout ensures compatibility with legacy space-qualified PCB layouts.

Use Value: Qualified per MIL-STD-883 assures performance after 100 krad(Si) TID exposure; 10-year retention supports multi-year orbital missions without refresh.

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AT28C256-90UM/883	Same 256-Kbit organization and 90 ns speed grade, but lacks page-write capability and software data protection; endurance rated at 10K cycles only.	Not suitable for systems requiring burst configuration updates or secure firmware locking; limited to static parameter storage.	Select only if page write and SDP are unnecessary and cost sensitivity outweighs feature loss.
MX28F256J3F-90U	32-pin PGA flash memory with 90 ns read, 100 µs page program time, and 100K endurance; requires sector erase before write.	Requires erase-before-write sequencing and longer latency for partial updates; incompatible with direct AT28HC256 pinout due to different control signal mapping.	Consider only for new designs where flash density and endurance justify redesign; not drop-in replaceable.

Compared with AT28HC256-90UM/883, AT28C256-90UM/883 omits page write and software protection-reducing flexibility in field updates-while MX28F256J3F-90U offers higher endurance but introduces erase complexity and timing incompatibility, making AT28HC256-90UM/883 optimal for legacy-maintained, security-critical, paged-write applications.

Availability

AT28HC256-90UM/883 is available at Aetrix Electronics and suitable for avionics control units, secure bootloader implementations, tactical radio firmware storage, and spacecraft telemetry configuration requiring stable component supply under extended military qualification.

Supply support for AT28HC256-90UM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with a focus on industrial, automotive, and aerospace markets.

The AT28HC256 product line delivers high-reliability parallel EEPROMs designed specifically for military and space applications demanding extended temperature operation, radiation tolerance, and deterministic write behavior.

FAQ

What is the maximum page write cycle time for AT28HC256-90UM/883?

The maximum page write cycle time for AT28HC256-90UM/883 is 10 ms, as specified in the AC characteristics table (tWC). This value applies across the full military temperature range (–55°C to +125°C) and represents the worst-case duration for internal programming of up to 64 bytes. The AT28HC256-90UM/883 does not support faster 3 ms write cycles-that variant is designated AT28HC256F and is not applicable to this part number.

Does AT28HC256-90UM/883 support software data protection, and how is it enabled?

Yes, AT28HC256-90UM/883 supports software data protection (SDP) via a three-step command sequence: write AAh to address 5555h, write 55h to address 2AAAh, then write A0h to address 5555h. After this sequence completes, all subsequent writes require repetition of the same sequence. The AT28HC256-90UM/883 ships with SDP disabled, and the feature remains active across power cycles until explicitly disabled using the 55h/2AAAh/80h/55h/2AAAh sequence.

What package type is used for AT28HC256-90UM/883, and what are its key mechanical features?

AT28HC256-90UM/883 uses a 30-pin Ceramic Pin Grid Array (PGA) package conforming to MIL-STD-1835 U-configuration. It features hermetically sealed ceramic construction, 2.54 mm pin pitch, 13.74 mm × 13.36 mm body dimensions, and gold-plated pins. The package is qualified for shock, vibration, and thermal cycling per MIL-STD-883, making it suitable for high-reliability aerospace and defense platforms where moisture ingress or mechanical stress is a concern.

How does DATA polling work on AT28HC256-90UM/883, and which pin is used?

DATA polling on AT28HC256-90UM/883 uses I/O7 to indicate write completion: during an active write cycle, reading the last written byte returns the bitwise complement of the data on I/O7; once the write finishes, true data appears on all I/O lines including I/O7. This mechanism allows the host processor to poll without halting other operations, and it functions independently of OE/CE/WE timing-making it ideal for interrupt-driven or time-critical systems using the AT28HC256-90UM/883.

Is AT28HC256-90UM/883 compatible with standard TTL and CMOS logic levels?

Yes, AT28HC256-90UM/883 has CMOS and TTL compatible inputs and outputs. Input thresholds meet VIH ≥ 2.0 V and VIL ≤ 0.8 V; output drive strength satisfies VOL ≤ 0.45 V at 6 mA sink and VOH ≥ 2.4 V at 4 mA source. These specifications ensure interoperability with legacy 5 V TTL systems and modern 5 V CMOS controllers without level-shifting circuitry-critical for maintaining signal integrity in mixed-logic avionics backplanes using the AT28HC256-90UM/883.

AT28HC256-90UM/883 Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 28-BCPGA

Packaging:: Box

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 256Kbit

Memory Organization:: 32K x 8

Memory Interface:: Parallel

Clock Frequency:: -

Write Cycle Time - Word, Page:: 10ms

Access Time:: 90 ns

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: -55°C ~ 125°C (TC)

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: 28-CPGA (13.97x16.51)

AT28HC256-90UM/883 FAQ

1.How can I place an order for AT28HC256-90UM/883 through Aetrix?

Please submit a Request for Quotation (RFQ) for AT28HC256-90UM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT28HC256-90UM/883 reliable?

The price and inventory of AT28HC256-90UM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256-90UM/883 is usually 5 days.

3.What payment methods are accepted for AT28HC256-90UM/883?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256-90UM/883 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT28HC256-90UM/883?

AT28HC256-90UM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT28HC256-90UM/883 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT28HC256-90UM/883?

For technical support, including AT28HC256-90UM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256-90UM/883 requirements.

6.How does Aetrix verify that AT28HC256-90UM/883 is sourced from the original manufacturer or authorized distributors?

All AT28HC256-90UM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256-90UM/883 meets industry standards.

7.What is the process for return or replacement of AT28HC256-90UM/883?

All AT28HC256-90UM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256-90UM/883, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT28HC256-90UM/883 part is unused and in its original packaging.

Return procedure for AT28HC256-90UM/883:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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