Microchip Technology AT28HC256E-12FM/883
- Part No.:
- AT28HC256E-12FM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-CFlatPack
- Datasheet:
-
AT28HC256E-12FM/883.pdf
- Description:
- IC EEPROM 256KBIT PAR 28FLATPK
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28HC256E-12FM/883 from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 120 ns read access time, 10 ms maximum page write cycle time, and full operation across –55°C to +125°C. It supports hardware/software data protection, DATA polling and toggle-bit write completion detection, and is used in avionics control modules requiring nonvolatile memory with radiation-tolerant packaging and MIL-STD-883 qualification.
For engineers reviewing the AT28HC256E-12FM/883 datasheet, AT28HC256E-12FM/883 pinout, AT28HC256E-12FM/883 application, or AT28HC256E-12FM/883 equivalent, this page delivers verified military-spec timing, endurance (100,000 cycles), JEDEC byte-wide pinout compliance, and exact package mapping for CERDIP/CLCC/Flatpack/PGA variants - critical for DO-254-compliant system integration and legacy aerospace board refresh.
Technical Context
The AT28HC256E-12FM/883 implements a paged architecture with a 64-byte internal latch, enabling 1–64-byte writes within a single 10 ms internal programming period. Its dual-line chip enable (CE) and output enable (OE) logic supports bus contention avoidance in multiprocessor systems, while VCC sense and 5 ms power-on delay circuitry prevent inadvertent writes during power ramp.
It features two independent write completion verification methods: DATA Polling on I/O7 (complement-to-data during write, true data upon completion) and toggle-bit monitoring on I/O6, both usable at any point during tWC. The device includes 64 bytes of dedicated identification EEPROM accessible via A9 = 12 V and addresses 7FC0H–7FFFH.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Capacity | 256 Kbit (32,768 × 8 words); enables storage of firmware boot code or configuration tables in space-constrained military controllers. |
| Read Access Time | 120 ns max; meets timing budgets for 8 MHz Z80 or 68000-based avionics processors without wait states. |
| Page Write Cycle Time | 10 ms max; allows full 64-byte page update within deterministic latency for real-time parameter logging. |
| Endurance | 100,000 write/erase cycles; supports >10 years of daily reconfiguration in ground-test equipment. |
| Data Retention | 10 years at +125°C; validated for unpowered storage in missile guidance canisters exposed to desert thermal cycling. |
| Supply Voltage | 5 V ±10%; compatible with legacy MIL-STD-704A regulated power buses without external regulation. |
| Operating Temperature | –55°C to +125°C; qualified per MIL-STD-883 Method 1010.8 for hermetic ceramic packages. |
Pinout & Package
AT28HC256E-12FM/883 is supplied in 32-lead CERDIP (MIL-STD-1835 D-10 Config A), with pins 1 and 17 designated "Don't Connect" per datasheet DS20006352A-page 4. Pin functions are JEDEC byte-wide compliant and identical across CERDIP, CLCC, Flatpack, and PGA variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte writes. |
| I/O0–I/O7 | Bidirectional Data Bus | CMOS/TTL-compatible 8-bit data path; I/O7 provides DATA Polling status, I/O6 provides toggle-bit status. |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; initiates write when pulsed low with OE high. |
| OE | Output Enable | Active-low output gate; controls bus drive; high during write operations to avoid contention. |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; rising edge triggers internal write timer. |
| VCC | Power Supply | +5 V ±10% supply; internal VCC sense disables writes below 3.8 V to prevent partial programming. |
| GND | Ground Reference | Signal and power return; decoupling required within 10 mm of VCC pin per MIL-PRF-38535 Class K layout rules. |
| DC / NC | No Connect / Don't Connect | Pins 1 and 17 (CERDIP) are unconnected; must remain floating - no PCB trace or solder mask relief required. |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Three-byte unlock sequence (AAh/55h/A0h) enables/disable write protection; prevents accidental overwrites during power transients in flight-critical systems. |
| Hardware Write Inhibit | VCC sense + 5 ms power-on delay + noise filtering (<15 ns pulses rejected) ensures zero spurious writes during cold-start or EMI events. |
| 64-Byte Identification Area | Dedicated EEPROM block at 7FC0H–7FFFH, accessible with A9 = 12 V; stores unit serial number, calibration date, and firmware revision for field traceability. |
| Page Write Architecture | Internal 64-byte latch frees address/data bus after first byte load; enables background processing during 10 ms internal programming window. |
| JEDEC Byte-Wide Pinout | Pin-compatible with industry-standard 28-pin EPROMs and EEPROMs; allows drop-in replacement in legacy 8086/8088-based test equipment designs. |
Applications
| Avionics Flight Control Unit | Tactical Radio Firmware Storage |
|---|---|
Use Scenario: Storing real-time trim parameters and sensor calibration coefficients updated during pre-flight checks. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced directly to Motorola 68332 CPU via 8-bit data bus and discrete address decoding. Use Value: 100,000-cycle endurance ensures >20 years of daily updates; 120 ns access eliminates wait states in 8 MHz bus timing. | Use Scenario: Holding encrypted waveform definitions and channel maps loaded during secure key exchange. IC Role / Device Role / Timing Role: Secure boot memory holding decryption keys and radio personality files; accessed only during initialization. Use Value: Hardware write inhibit prevents corruption during RF-induced power droop; MIL-STD-883 screening guarantees reliability in jamming environments. |
| Missile Guidance System | Ground Test Equipment Calibration |
Use Scenario: Retaining mission-specific targeting vectors and inertial navigation offsets across launch cycles. IC Role / Device Role / Timing Role: Radiation-hardened nonvolatile memory storing mission-critical constants; operates at full spec under thermal shock. Use Value: 10-year data retention at +125°C ensures integrity during extended storage in desert deployment; CERDIP hermeticity blocks moisture ingress. | Use Scenario: Logging calibration coefficients and sensor linearity corrections for automated test sets. IC Role / Device Role / Timing Role: Field-updatable reference memory storing NIST-traceable correction tables; rewritten monthly during metrology audits. Use Value: Page write capability reduces update time from seconds to <15 ms; DATA polling enables deterministic host software synchronization. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC256-12JU | Same die, 32-lead CLCC package; no MIL-STD-883 qualification; commercial temperature range (0°C to +70°C). | Suitable for lab prototypes or non-mission-critical ground support equipment where cost and lead time outweigh environmental requirements. | Select only if MIL-STD-883 screening, extended temperature, or hermetic packaging is not required. |
| DS2502-E48+ | 1-Wire interface EEPROM; 1 Kbit capacity; no parallel bus; 100 kcycles endurance; industrial temp (–40°C to +85°C). | Used in distributed sensor nodes where wiring minimization and daisy-chaining are prioritized over speed and density. | Not a functional substitute: serial interface, lower density, and incompatible timing model preclude direct replacement. |
Compared with AT28HC256E-12FM/883, AT28HC256-12JU offers identical electrical behavior but lacks military screening and extended temperature validation, while DS2502-E48+ trades parallel speed and density for 1-Wire simplicity - making neither a drop-in alternative for avionics or guided weapon systems requiring MIL-PRF-38535 Class K assurance.
Availability
AT28HC256E-12FM/883 is available at Aetrix Electronics and suitable for avionics flight control units, tactical radio firmware storage, missile guidance systems, and ground test equipment calibration requiring stable component supply under ITAR-controlled logistics and long-lifecycle procurement.
Supply support for AT28HC256E-12FM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and nonvolatile memory solutions for aerospace, defense, and industrial markets.
The AT28HC256 product line delivers radiation-tolerant, high-reliability parallel EEPROMs designed specifically for legacy military platforms requiring MIL-STD-883 qualification, hermetic packaging, and deterministic write timing - bridging obsolescence gaps in 1980s–1990s avionics architectures.
FAQ
What is the maximum operating temperature range for the AT28HC256E-12FM/883?
The AT28HC256E-12FM/883 is fully specified and tested from –55°C to +125°C per MIL-STD-883 Method 1010.8. This extended range is achieved through hermetic CERDIP packaging and process-level screening, enabling use in engine-mounted sensors and missile canisters where ambient temperatures exceed commercial limits. The AT28HC256E-12FM/883 maintains all AC/DC specifications across this full range without derating.
Does the AT28HC256E-12FM/883 support page write operations, and what is the maximum page size?
Yes, the AT28HC256E-12FM/883 supports page write operations with a fixed 64-byte page size. Up to 64 bytes can be loaded sequentially within 150 µs of each other (tBLC), after which the internal timer initiates programming. The AT28HC256E-12FM/883 uses A6–A14 to define the page address; all bytes in a given page write must share identical A6–A14 values, while A0–A5 select individual byte positions within that page.
How is write completion detected on the AT28HC256E-12FM/883?
The AT28HC256E-12FM/883 provides two independent, hardware-verified methods: DATA Polling on I/O7 (returns complement of last written byte until complete, then true data) and Toggle Bit monitoring on I/O6 (toggles between 0 and 1 during programming, stabilizes upon completion). Both methods are usable at any time during the 10 ms write cycle and require no additional timing margins. The AT28HC256E-12FM/883 does not require external polling delays or fixed timeouts.
What package type is used for the AT28HC256E-12FM/883, and are pins 1 and 17 connected?
The AT28HC256E-12FM/883 is packaged in a 32-lead CERDIP (MIL-STD-1835 D-10 Config A) with hermetic glass-sealed construction. Per datasheet DS20006352A-page 4, pins 1 and 17 are explicitly designated "Don't Connect" - they are unconnected internally and must remain floating on the PCB. No trace, pad, or solder mask relief is permitted on these pins per MIL-PRF-38535 Class K assembly requirements.
Is software data protection enabled by default on the AT28HC256E-12FM/883, and how is it activated?
No, software data protection (SDP) is disabled by default on the AT28HC256E-12FM/883. It is activated by writing the three-byte unlock sequence: AAh to address 5555h, 55h to address 2AAAh, then A0h to address 5555h. Once enabled, all subsequent writes require repeating this sequence before data. The AT28HC256E-12FM/883 retains SDP state across power cycles, and the disable sequence (AAh/55h/80h/AAh/20h/55h/2AAAh) must be issued to deactivate it.
AT28HC256E-12FM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-CFlatPack
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-FlatPack, Ceramic Bottom-Brazed
AT28HC256E-12FM/883 FAQ
1.How can I place an order for AT28HC256E-12FM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256E-12FM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256E-12FM/883 reliable?
The price and inventory of AT28HC256E-12FM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256E-12FM/883 is usually 5 days.
3.What payment methods are accepted for AT28HC256E-12FM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256E-12FM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256E-12FM/883?
AT28HC256E-12FM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256E-12FM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256E-12FM/883?
For technical support, including AT28HC256E-12FM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256E-12FM/883 requirements.
6.How does Aetrix verify that AT28HC256E-12FM/883 is sourced from the original manufacturer or authorized distributors?
All AT28HC256E-12FM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256E-12FM/883 meets industry standards.
7.What is the process for return or replacement of AT28HC256E-12FM/883?
All AT28HC256E-12FM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256E-12FM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256E-12FM/883 part is unused and in its original packaging.
Return procedure for AT28HC256E-12FM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256E-12FM/883 Tags

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