Microchip Technology AT28HC256E-12SU
- Part No.:
- AT28HC256E-12SU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28HC256E-12SU.pdf
- Description:
- IC EEPROM 256KBIT PAR 28SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,876
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256E-12SU from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 120 ns read access time, 10 ms maximum page write cycle, CMOS/TTL-compatible I/O, and full −55°C to +125°C operation. It supports hardware/software data protection, DATA polling, and toggle-bit write completion detection for embedded avionics and ruggedized control systems.
For engineers reviewing the AT28HC256E-12SU datasheet, AT28HC256E-12SU pinout, AT28HC256E-12SU application, or AT28HC256E-12SU equivalent, key selection considerations include its JEDEC-standard 32-lead CERDIP package, 5V ±10% single-supply operation, 100,000 write endurance, 10-year data retention, and military temperature compliance - critical for high-reliability program storage in defense electronics.
Technical Context
The AT28HC256E-12SU implements a paged architecture with a 64-byte internal latching register, enabling 1–64 byte writes per internal programming cycle. Its dual-line chip enable (CE) and output enable (OE) control allows bus contention avoidance in shared-memory systems.
It integrates VCC sense circuitry (write inhibit below 3.8 V), 5 ms power-on delay, noise filtering on WE/CE (<15 ns pulses rejected), and optional software data protection via three-step command sequence (AAh/55h/A0h) to prevent inadvertent writes during power transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 256 Kbit (32,768 × 8) - provides nonvolatile storage for firmware boot code or configuration tables in space-constrained military platforms |
| Read Access Time | 120 ns - meets timing requirements for direct interface with legacy 8-bit microcontrollers operating at ≤8 MHz |
| Page Write Cycle Time | 10 ms maximum - enables efficient bulk parameter updates without requiring external wait-state logic |
| Write Endurance | 100,000 cycles - supports field-updatable calibration data logging in test equipment and telemetry systems |
| Data Retention | 10 years at +125°C - ensures long-term integrity of mission-critical configuration data in sealed avionics enclosures |
| Supply Voltage | 5 V ±10% - compatible with standard MIL-STD-704A aircraft power buses and industrial 5 V rails |
| Operating Temperature | −55°C to +125°C - qualified for deployment in engine-mounted controllers and missile guidance subsystems |
Pinout & Package
AT28HC256E-12SU is supplied in a 32-lead CERDIP (Ceramic Dual Inline Package) with 0.600" width, glass-sealed construction per MIL-STD-1835 D-10 Config A. Pin 1 is index-marked; pins 1 and 17 are "Don't Connect" (DC) per CLCC variant compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32,768-word addressing; A6–A14 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional Data Bus | CMOS/TTL-compatible 8-bit data path; I/O7 used for DATA polling, I/O6 for toggle-bit status indication |
| CE | Chip Enable | Active-low device select; must be low with OE low and WE high for read access; initiates write when low with OE high |
| OE | Output Enable | Active-low output gate; controls data bus drive; high-Z state prevents bus contention during write cycles |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; combined with CE for robust write initiation in noisy environments |
| VCC | Power Supply | +5 V ±10% supply; internal VCC sense disables writes below ~3.8 V to prevent corruption during brownout |
| GND | Ground Reference | Signal and power ground return; decoupling capacitor required within 10 mm of VCC pin per MIL-PRF-38535 |
| NC / DC | No Connect / Don't Connect | Pins 1 and 17 are unconnected; must remain floating - no routing or soldering permitted |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Data Protection | VCC sensing, 5 ms power-on delay, and noise-filtered WE/CE inputs eliminate need for external reset supervisors in MIL-STD-704A power systems |
| Software Data Protection (SDP) | User-enabled 3-byte unlock sequence (AAh/55h/A0h) prevents accidental writes during firmware updates or field maintenance |
| Page Write Architecture | 64-byte internal latch allows burst programming without CPU intervention - reduces host processor overhead by >90% vs. byte-write mode |
| End-of-Write Detection | Dual methods: DATA polling on I/O7 (complement → true data transition) and toggle-bit on I/O6 - enables deterministic polling without fixed delays |
| Military Qualification | Qualified to MIL-PRF-38535 Class K; includes 64-byte device ID area accessible at 7FC0h–7FFFh with A9 = 12 V for traceability and anti-counterfeiting |
Applications
| Avionics Boot Memory | Tactical Radio Configuration Storage |
|---|---|
Use Scenario: Stores bootloader firmware and FPGA configuration bitstreams in airborne mission computers where radiation tolerance and thermal cycling resilience are mandatory. IC Role / Device Role / Timing Role: Nonvolatile program memory mapped into microprocessor address space; accessed as SRAM-equivalent during cold start and warm reset sequences. Use Value: 120 ns read timing ensures zero-wait-state execution from reset vector; 100,000-cycle endurance supports in-field reprogramming of mission-specific payloads. | Use Scenario: Holds encryption keys, frequency plans, and network topology parameters in manpack and vehicular radios deployed across desert and arctic environments. IC Role / Device Role / Timing Role: Secure configuration store with software data protection enabled; write operations gated by SDP unlock sequence to prevent RF-induced corruption. Use Value: −55°C to +125°C operation eliminates derating concerns; 10-year data retention guarantees key validity over full equipment lifecycle without battery backup. |
| Missile Guidance System Calibration | Naval Sonar Signal Processing Firmware |
Use Scenario: Stores factory-calibrated sensor offsets and gain coefficients in inertial measurement units mounted on high-G launch platforms. IC Role / Device Role / Timing Role: High-reliability parameter memory; accessed via dedicated DMA channel during pre-launch self-test; write-protected except during depot-level recalibration. Use Value: Hardware VCC-sense protection prevents write corruption during rapid power transients induced by rocket motor ignition. | Use Scenario: Stores adaptive beamforming coefficients and acoustic signature templates in hull-mounted sonar arrays exposed to salt fog and shock loading. IC Role / Device Role / Timing Role: Field-updatable firmware repository; page write mode enables full coefficient set reload in <10 ms without interrupting real-time signal processing. Use Value: 32-lead CERDIP package withstands 50 g shock per MIL-S-901D; 10 ms write cycle aligns with sonar ping interval scheduling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC256-12JC | Same core die, but 28-lead CERDIP package; lacks military temp rating (0°C to +70°C only); no MIL-PRF-38535 qualification | Restricted to commercial ground-based test equipment; unsuitable for flight or shipboard use | Select only for cost-sensitive lab instruments where extended temperature range is unnecessary |
| MX28F256KXCB-12 | Intel-compatible 256 Kbit parallel EEPROM; 120 ns access; 32-lead PLCC package; 10,000-cycle endurance (not 100,000) | Limited reprogrammability in field-deployed systems requiring frequent calibration updates | Acceptable for static configuration storage where update frequency is <100× over product lifetime |
Compared with AT28HC256-12JC and MX28F256KXCB-12, the AT28HC256E-12SU delivers military-grade reliability through its −55°C to +125°C operation, 100,000-cycle endurance, and MIL-PRF-38535 Class K qualification - making it the sole option for safety-critical, field-reprogrammable memory in defense electronics.
Availability
AT28HC256E-12SU is available at Aetrix Electronics and suitable for avionics boot memory, tactical radio configuration storage, missile guidance system calibration, and naval sonar signal processing firmware requiring stable component supply across extended military procurement cycles.
Supply support for AT28HC256E-12SU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with a strong heritage in military and aerospace components.
The AT28HC256E-12SU belongs to Microchip's high-reliability parallel EEPROM product line, designed specifically for nonvolatile storage in harsh-environment applications where extended temperature operation, long data retention, and immunity to power-supply transients are essential.
FAQ
What is the maximum page write cycle time for the AT28HC256E-12SU?
The AT28HC256E-12SU has a maximum page write cycle time of 10 ms. This value applies to the E-grade (100,000-cycle endurance) variant and is verified under worst-case conditions across the full −55°C to +125°C temperature range. The AT28HC256E-12SU uses an internal control timer to complete the write autonomously after the final byte is latched, eliminating the need for external timing circuitry.
How does software data protection work on the AT28HC256E-12SU?
Software data protection on the AT28HC256E-12SU is enabled via a three-step command sequence: write AAh to address 5555h, 55h to 2AAAh, then A0h to 5555h. Once activated, all subsequent writes require repeating this sequence before data. The AT28HC256E-12SU retains protection across power cycles, and the feature is shipped disabled. Disabling uses a separate five-step sequence (AAh/55h/80h/AAh/20h).
Which package type is used by the AT28HC256E-12SU?
The AT28HC256E-12SU uses a 32-lead CERDIP (Ceramic Dual Inline Package) with 0.600" width and glass-sealed construction compliant with MIL-STD-1835 D-10 Config A. Pins 1 and 17 are designated "Don't Connect" and must remain unconnected. This package provides hermetic sealing and thermal stability required for military deployment.
Can the AT28HC256E-12SU operate with a 3.3 V supply?
No, the AT28HC256E-12SU requires a single 5 V ±10% supply (4.5 V to 5.5 V) and is not rated for 3.3 V operation. Its internal VCC sense circuit inhibits writes below ~3.8 V, and DC characteristics such as VOL, VOH, and ICC are specified only at 5 V. Using 3.3 V will result in undefined behavior, failed writes, and potential data corruption.
What is the purpose of the 64-byte device identification area in the AT28HC256E-12SU?
The AT28HC256E-12SU includes a dedicated 64-byte device identification area at addresses 7FC0h–7FFFh, accessible by raising A9 to 12.0 V ±0.5 V. This area supports permanent serialization, lot traceability, and anti-counterfeiting in defense supply chains. Unlike main array writes, programming this region requires elevated voltage and follows distinct timing - ensuring separation from functional memory operations.
AT28HC256E-12SU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28HC256E-12SU FAQ
1.How can I place an order for AT28HC256E-12SU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256E-12SU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256E-12SU reliable?
The price and inventory of AT28HC256E-12SU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256E-12SU is usually 5 days.
3.What payment methods are accepted for AT28HC256E-12SU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256E-12SU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256E-12SU?
AT28HC256E-12SU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256E-12SU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256E-12SU?
For technical support, including AT28HC256E-12SU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256E-12SU requirements.
6.How does Aetrix verify that AT28HC256E-12SU is sourced from the original manufacturer or authorized distributors?
All AT28HC256E-12SU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256E-12SU meets industry standards.
7.What is the process for return or replacement of AT28HC256E-12SU?
All AT28HC256E-12SU units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256E-12SU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256E-12SU part is unused and in its original packaging.
Return procedure for AT28HC256E-12SU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256E-12SU Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

