My Inquiry
My Account
Microchip Technology AT28HC256E-90LM/883
- Part No.:
- AT28HC256E-90LM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-CLCC
- Datasheet:
-
AT28HC256E-90LM/883.pdf
- Description:
- IC EEPROM 256KBIT PARALLEL 32LCC
- Quantity:
- Payment:
- Shipping:
Inventory:4,934
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256E-90LM/883 from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 90 ns read access time, 10 ms maximum page write cycle time, and full operation across –55°C to +125°C. It features hardware/software data protection, DATA polling and toggle-bit write completion detection, and operates from a single 5V ±10% supply. It is used in avionics control modules requiring nonvolatile storage with deterministic timing and radiation-tolerant reliability.
For engineers reviewing the AT28HC256E-90LM/883 datasheet, AT28HC256E-90LM/883 pinout, AT28HC256E-90LM/883 application, or AT28HC256E-90LM/883 equivalent, this page delivers verified military-spec electrical parameters, JEDEC-compliant byte-wide pin mapping, endurance and retention specs, and real-world substitution guidance for high-reliability embedded systems design.
Technical Context
The AT28HC256E-90LM/883 implements a paged architecture with an internal 64-byte latch enabling simultaneous writes of 1–64 bytes per cycle. Its address space is organized as 32,768 × 8, with A0–A14 decoding the full 15-bit address; A6–A14 define the page boundary during page write operations.
It supports three write detection methods: DATA polling on I/O7 (complement-to-data during write), toggle-bit monitoring on I/O6, and software-controlled chip erase via 6-byte command sequence. Hardware protection includes VCC sense (<3.8 V inhibits write), 5 ms power-on delay, and noise filtering on WE/CE inputs (rejects <15 ns pulses).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory density | 256 Kbit (32,768 × 8) - provides sufficient nonvolatile storage for firmware boot code or configuration tables in compact military subsystems |
| Read access time | 90 ns - enables direct replacement of SRAM in legacy MIL-STD-1553 or discrete logic-based controllers without timing redesign |
| Page write cycle time | 10 ms max - defines worst-case latency for bulk parameter updates in flight control computers |
| Endurance | 10,000 write/erase cycles - validated for mission-critical reprogramming over extended service life under thermal cycling |
| Data retention | 10 years at +125°C - guarantees integrity of calibration constants and fault logs in sealed avionics enclosures |
| Supply voltage | 5 V ±10% - compatible with standard MIL-STD-704A aircraft power buses without regulation overhead |
| Operating temperature | –55°C to +125°C - meets MIL-PRF-38535 Class B requirements for surface-mount ceramic packages |
Pinout & Package
AT28HC256E-90LM/883 is supplied in a 32-pad CLCC (Ceramic Leadless Chip Carrier) package compliant with MIL-STD-1835 C-12. Pins 1 and 17 are designated "Don't Connect" per datasheet DS20006352A-page 4. All other pins follow JEDEC-standard byte-wide parallel interface layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus; A6–A14 select 64-byte page during write, A0–A5 select byte offset within page |
| I/O0–I/O7 | Bidirectional data bus | CMOS/TTL-compatible 8-bit parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit status |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; initiates write when toggled with OE high |
| OE | Output Enable | Active-low output gate; controls bus contention; must be high during write cycles |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; works with CE for dual-control write initiation |
| VCC | Power supply | +5 V ±10% main supply; internal VCC sense circuitry disables writes below ~3.8 V |
| GND | Ground reference | Signal and power return; decoupling required per MIL-STD-1553B layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| Page write with 64-byte internal latch | Reduces host CPU overhead by allowing burst loading of up to 64 bytes before internal programming begins |
| DATA polling on I/O7 | Enables deterministic write completion detection without timer polling or external status lines |
| Software data protection (SDP) | Prevents accidental writes via 3-byte unlock sequence (AAh/55h/A0h); persists through power cycles |
| Hardware write inhibit | Combines VCC sensing, 5 ms power-up delay, and noise filtering to eliminate spurious writes during brownout or EMI events |
| Device identification area | 64-byte reserved EEPROM block (7FC0h–7FFFh) accessible at 12 V on A9 for serialization or calibration data storage |
Applications
| Avionics Flight Control Unit | Military Radar Signal Processor |
|---|---|
Use Scenario: Storing real-time calibration coefficients and fault history logs in a fly-by-wire controller operating at –55°C to +125°C. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced directly to a MIL-STD-1553B bus controller's local bus; accessed synchronously with 90 ns timing budget. Use Value: Eliminates need for external write-protection logic or backup battery; 10-year data retention ensures log integrity across depot maintenance intervals. |
Use Scenario: Holding radar waveform templates and beam-steering lookup tables in a phased-array radar front-end module. IC Role / Device Role / Timing Role: Parallel EEPROM mapped into FPGA's configuration address space; page-write capability enables rapid table updates during mode switching. Use Value: 10 ms max page write time allows sub-frame reconfiguration; hardware/software protection prevents corruption during RF-induced transients. |
| Tactical Vehicle Engine Management | Secure Communications Crypto Module |
Use Scenario: Storing engine timing maps and emission calibration data in armored vehicle ECUs exposed to wide thermal excursions and vibration. IC Role / Device Role / Timing Role: Directly connected to 8051-based microcontroller bus; CE/OE/WE signals driven by discrete logic for deterministic timing control. Use Value: Ceramic CLCC package withstands mechanical shock; 10,000-cycle endurance supports field recalibration over 15+ year service life. |
Use Scenario: Storing cryptographic keys and algorithm version identifiers in NSA-certified Type 1 encryption hardware. IC Role / Device Role / Timing Role: Isolated nonvolatile memory partition accessed only during secure boot; protected via SDP and VCC-sense hardware lockout. Use Value: Dual-layer protection (hardware + software) prevents key overwrite during power faults or electromagnetic pulse (EMP) events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC256-90JU | Commercial-grade (0°C to +70°C), 32-pin TSSOP package, no MIL-PRF-38535 qualification | Lacks extended temperature range and radiation-hardened packaging; unsuitable for airborne or space-qualified designs | Select only for ground-based test equipment or non-mission-critical prototypes where cost outweighs environmental robustness |
| MX28F256KDT | Intel-compatible 256 Kbit flash memory; requires sector erase before write; no page write or DATA polling | Higher endurance (100K cycles) but slower effective write throughput due to mandatory erase step | Choose when system architecture already uses flash-based firmware storage and can accommodate erase latency; not drop-in compatible |
Compared with AT28HC256E-90LM/883, AT28HC256-90JU sacrifices military temperature range and hermeticity for lower cost and smaller footprint, while MX28F256KDT trades deterministic page-write timing for higher endurance and flash compatibility-neither offers pin-for-pin or functional equivalence in MIL-STD-1553 or avionics control environments.
Availability
AT28HC256E-90LM/883 is available at Aetrix Electronics and suitable for avionics flight control units, military radar signal processors, tactical vehicle engine management systems, and secure communications crypto modules requiring stable component supply under extended temperature and long-lifecycle conditions.
Supply support for AT28HC256E-90LM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with a strong heritage in military and aerospace components following its acquisition of Atmel.
The AT28HC256 product line was originally developed by Atmel and continues under Microchip to serve high-reliability embedded systems requiring radiation-tolerant, temperature-stable, and long-retention nonvolatile memory for defense and space applications.
FAQ
What is the guaranteed minimum endurance rating for AT28HC256E-90LM/883?
The AT28HC256E-90LM/883 is rated for a minimum of 10,000 write/erase cycles under full military temperature range (–55°C to +125°C) and 5 V ±10% supply conditions. This endurance is validated per MIL-PRF-38535 screening and applies to both byte and page write operations. The device also supports optional extended endurance (100,000 cycles) in non-military variants, but AT28HC256E-90LM/883 specifically conforms to the 10K specification.
Does AT28HC256E-90LM/883 support true 90 ns read access across its entire military temperature range?
Yes. The AT28HC256E-90LM/883 guarantees 90 ns maximum read access time (tACC and tCE) across –55°C to +125°C, as specified in Table 6-2 of DS20006352A. This includes all DC and AC operating conditions defined for the -90 speed grade, with VCC = 5 V ±10%. No derating or timing margin adjustment is required for operation at temperature extremes.
How is software data protection enabled on AT28HC256E-90LM/883?
Software data protection (SDP) on AT28HC256E-90LM/883 is enabled by writing three specific bytes to three specific addresses: AAh to address 5555h, 55h to address 2AAAh, then A0h to address 5555h. After this sequence, all subsequent writes require repetition of the same unlock sequence. The AT28HC256E-90LM/883 ships with SDP disabled, and the feature remains active across power cycles until explicitly disabled using the 5-byte disable algorithm.
What package type does AT28HC256E-90LM/883 use, and are pins 1 and 17 connected?
AT28HC256E-90LM/883 uses a 32-pad CLCC (Ceramic Leadless Chip Carrier) package per MIL-STD-1835 C-12. As confirmed in DS20006352A-page 4, pins 1 and 17 are designated "Don't Connect" and must remain unconnected in PCB layout. All other pins follow JEDEC-standard byte-wide parallel interface mapping, including dedicated address (A0–A14), data (I/O0–I/O7), and control (CE, OE, WE, VCC, GND) functions.
Can AT28HC256E-90LM/883 perform page writes across multiple pages in a single operation?
No. AT28HC256E-90LM/883 restricts each page write operation to a single 64-byte page, defined by the state of address lines A6–A14. During a page write, A6–A14 must remain constant across all WE high-to-low transitions; changing them mid-sequence terminates the page load and starts internal programming. To write across multiple pages, separate page write cycles must be initiated, each with its own A6–A14 setup and 10 ms (max) programming window.
AT28HC256E-90LM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-CLCC
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-LCC (11.43x13.97)
AT28HC256E-90LM/883 FAQ
1.How can I place an order for AT28HC256E-90LM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256E-90LM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256E-90LM/883 reliable?
The price and inventory of AT28HC256E-90LM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256E-90LM/883 is usually 5 days.
3.What payment methods are accepted for AT28HC256E-90LM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256E-90LM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256E-90LM/883?
AT28HC256E-90LM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256E-90LM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256E-90LM/883?
For technical support, including AT28HC256E-90LM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256E-90LM/883 requirements.
6.How does Aetrix verify that AT28HC256E-90LM/883 is sourced from the original manufacturer or authorized distributors?
All AT28HC256E-90LM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256E-90LM/883 meets industry standards.
7.What is the process for return or replacement of AT28HC256E-90LM/883?
All AT28HC256E-90LM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256E-90LM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256E-90LM/883 part is unused and in its original packaging.
Return procedure for AT28HC256E-90LM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256E-90LM/883 Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
