Microchip Technology AT28HC256E-90PU

Overview

AT28HC256E-90PU from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 90 ns read access time, 10 ms maximum page write cycle, CMOS/TTL-compatible I/O, and full −55°C to +125°C operation. It supports hardware/software data protection and DATA Polling for write completion detection in avionics control and ruggedized instrumentation systems.

For engineers reviewing the AT28HC256E-90PU datasheet, AT28HC256E-90PU pinout, AT28HC256E-90PU application, or AT28HC256E-90PU equivalent, key selection considerations include military temperature compliance, 64-byte page write capability, JEDEC-standard 32-lead CERDIP package, and VCC-sense write inhibit for power-transition safety.

Technical Context

The AT28HC256E-90PU implements a paged architecture with an internal 64-byte latch and autonomous control timer, enabling 1–64 byte writes without external timing circuitry. Its dual-line chip enable (CE) and output enable (OE) logic allows flexible bus contention management in multi-master embedded systems.

It features both DATA Polling (I/O7 complement toggle) and Toggle Bit (I/O6 oscillation) mechanisms for non-blocking write status monitoring, alongside hardware-level VCC sense (<3.8 V inhibition) and noise filtering (<15 ns pulse rejection) to prevent spurious writes during power-up/down sequences.

Key Specifications

Pinout & Package

AT28HC256E-90PU is supplied in a 32-lead CERDIP (Ceramic Dual Inline Package) with 0.600" width, MIL-STD-1835 D-10 Config A glass-sealed construction. Pin 1 is index-marked; pins 1 and 17 are "Don't Connect" (DC) per datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar EEPROM applications.

Compared with AT28HC256E-90PU, AT28HC256-90JU offers identical functionality in a lower-cost PLCC but lacks military qualification, while MX28F256KXCB-90 trades page-write convenience for higher density and longer endurance at the cost of mandatory erase-before-write sequencing.

Availability

AT28HC256E-90PU is available at Aetrix Electronics and suitable for avionics control units, missile guidance subsystems, and ruggedized industrial PLCs requiring stable component supply under extended temperature and long-lifecycle procurement programs.

Supply support for AT28HC256E-90PU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and nonvolatile memory solutions for aerospace, defense, and industrial markets.

The AT28HC256 product line delivers radiation-tolerant, high-reliability parallel EEPROMs designed specifically for MIL-STD-1553 bus interfaces, flight-critical data logging, and secure configuration storage in harsh environments.

FAQ

What is the guaranteed minimum read access time for AT28HC256E-90PU?

The AT28HC256E-90PU guarantees a maximum read access time of 90 ns under military temperature and voltage conditions (−55°C to +125°C, VCC = 4.5 V to 5.5 V). This value is fully tested and specified in Table 6-2 of the DS20006352A datasheet. The 90 ns rating applies to both CE-to-output and address-to-output delays, ensuring deterministic timing for real-time avionics bus arbitration. AT28HC256E-90PU meets this specification across its entire qualified temperature range without derating.

Does AT28HC256E-90PU support true page write operations, and what is the maximum page size?

Yes, AT28HC256E-90PU supports true internal page write operations with a fixed 64-byte page size. During a page write, the device internally latches up to 64 bytes of data and executes the programming sequence autonomously using its internal control timer. Each byte must be loaded within 150 µs of the prior byte (tBLC), and all addresses must reside on the same page defined by A6–A14. AT28HC256E-90PU completes the full 64-byte write in ≤10 ms, eliminating CPU intervention during programming.

How does hardware write protection function in AT28HC256E-90PU?

AT28HC256E-90PU implements three hardware write protection mechanisms: (1) VCC sense circuitry disables writes when supply drops below 3.8 V, (2) a 5 ms power-on delay timer prevents writes until VCC stabilizes, and (3) noise filtering rejects input pulses <15 ns on WE or CE. These features operate independently of software control and are active at all times - including power-up, power-down, and brown-out events. AT28HC256E-90PU uses these circuits to meet MIL-STD-704E transient immunity requirements without external supervision.

Can AT28HC256E-90PU be used as a direct replacement for standard SRAM in existing designs?

AT28HC256E-90PU is pin-compatible with many 32K × 8 SRAMs (e.g., IS61LV256AL) in read mode and shares JEDEC-standard byte-wide pinout, but it is not a functional drop-in replacement due to write timing differences and lack of true random-write capability. While reads mirror SRAM behavior, writes require explicit page management and status polling. AT28HC256E-90PU can replace SRAM only when the host controller implements DATA Polling or Toggle Bit monitoring and adheres to tBLC and tWC timing constraints.

What package type is used for AT28HC256E-90PU, and are there any special handling requirements?

AT28HC256E-90PU is packaged in a 32-lead CERDIP (Ceramic Dual Inline Package) with glass-sealed MIL-STD-1835 D-10 Config A construction. Pins 1 and 17 are designated "Don't Connect" and must remain unconnected - no routing, grounding, or capacitive loading is permitted. The package requires conformal coating per MIL-I-46058C Class 3 for humidity resistance in marine or high-altitude deployments. AT28HC256E-90PU must be handled per J-STD-020 moisture sensitivity level 1, with no bake requirement prior to soldering.