Microchip Technology AT28HC256F-90DM/883
- Part No.:
- AT28HC256F-90DM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-CDIP (0.600", 15.24mm)
- Datasheet:
-
AT28HC256F-90DM/883.pdf
- Description:
- IC EEPROM 256KBIT PAR 28CERDIP
- Quantity:
- Payment:

- Shipping:

Inventory:2,694
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256F-90DM/883 from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 90 ns read access time, 3 ms maximum page write cycle time, and full operation across –55°C to +125°C. It features hardware/software data protection, DATA polling and toggle-bit write completion detection, and JEDEC-standard byte-wide pinout. Used in avionics control modules for nonvolatile configuration storage requiring radiation-tolerant, long-retention memory.
For engineers reviewing the AT28HC256F-90DM/883 datasheet, AT28HC256F-90DM/883 pinout, AT28HC256F-90DM/883 application, or AT28HC256F-90DM/883 equivalent, this page delivers verified military-spec timing, endurance (10,000 cycles), power behavior (80 mA active / 300 µA CMOS standby), and package-specific pin validation for CERDIP/CLCC/FLATPACK/PGA variants.
Technical Context
The AT28HC256F-90DM/883 implements a paged architecture with a 64-byte internal latch, enabling simultaneous write of 1–64 bytes within a single page defined by address bits A6–A14. Its dual-line chip enable (CE) and output enable (OE) control supports bus contention avoidance in multiprocessor systems.
Write operations are governed by an internal control timer; completion is signaled via I/O7 DATA polling or I/O6 toggle-bit behavior. Hardware protection includes VCC sense (<3.8 V inhibits writes), 5 ms power-on delay, noise filtering (<15 ns pulses ignored), and write-inhibit logic (OE low, CE high, or WE high).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 256 Kbit (32,768 × 8) - provides sufficient space for boot code, calibration tables, and fault logs in embedded military systems. |
| Read access time | 90 ns - enables direct replacement of SRAM in legacy MIL-STD-1553 or ARINC-429 interface controllers without timing redesign. |
| Page write cycle time | 3 ms max - reduces firmware update latency vs. 10 ms standard variant, critical for field-programmable mission profiles. |
| Endurance | 10,000 write/erase cycles - validated for repeated reconfiguration in ground support equipment and flight test instrumentation. |
| Data retention | 10 years at +125°C - meets MIL-PRF-38535 Class B requirements for unpowered storage in sealed avionics enclosures. |
| Supply voltage | 5 V ±10% - compatible with legacy 5 V TTL/CMOS logic families without level-shifting circuitry. |
| Operating temperature | –55°C to +125°C - qualified per MIL-STD-883 Method 1010 for extended thermal cycling in missile guidance subsystems. |
Pinout & Package
AT28HC256F-90DM/883 is supplied in 32-lead CERDIP, 32-lead CLCC, 32-lead FLATPACK, and 30-pin PGA packages. Pin functions are identical across all variants per JEDEC byte-wide standard; pin 1 orientation and mechanical dimensions differ per package type.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus supporting full 32,768-word addressing; A6–A14 define page boundaries for 64-byte write operations. |
| I/O0–I/O7 | Bidirectional data bus | CMOS/TTL-compatible 8-bit parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit write status indication. |
| CE | Chip Enable | Active-low device select; must be low with OE low and WE high for read access; initiates write when low with OE high and WE low. |
| OE | Output Enable | Active-low output gate; controls data bus drive during reads; high during writes to prevent bus contention. |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; rising edge triggers internal write timer and page programming sequence. |
| VCC | Power supply | +5 V ±10% primary supply; internal VCC sense circuitry disables writes below ~3.8 V to prevent corruption during brownout. |
| GND | Ground reference | Signal and power return path; decoupling capacitor placement near pin 14 (CERDIP) or pin 16 (CLCC) required for stable 90 ns timing. |
| NC / DC | No-connect / Don't connect | Pins marked NC or DC (e.g., CLCC pins 1 & 17) must remain unconnected; floating these pins prevents parasitic coupling in high-noise EMI environments. |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte page register | Enables burst writes without external address sequencing logic - reduces MCU GPIO overhead and firmware complexity in telemetry recorders. |
| DATA Polling (I/O7) | Provides deterministic, clock-synchronous write completion detection - eliminates need for fixed-delay loops or external timers in real-time OS tasks. |
| Toggle Bit (I/O6) | Offers asynchronous, interrupt-driven write status monitoring - allows CPU to perform other tasks while waiting for EEPROM programming to finish. |
| Software Data Protection (SDP) | Three-byte command sequence (AAh/55h/A0h) enables/disable write lock - prevents accidental overwrites during power-up transients in airborne power management units. |
| Extra 64-byte ID area | Accessible via A9 = 12 V ±0.5 V at addresses 7FC0h–7FFFh - stores unique unit serial numbers, calibration coefficients, or firmware version stamps traceable to MIL-STD-130. |
Applications
| Avionics Boot Memory | Mission Data Logger |
|---|---|
|
Use Scenario: Stores bootloader firmware and FPGA configuration bitstreams in radar signal processors deployed on fighter aircraft. IC Role / Device Role / Timing Role: Nonvolatile storage element interfaced directly to a 5 V Z80 or 80C86 host processor; operates as memory-mapped peripheral with static RAM timing compatibility. Use Value: 90 ns access ensures no wait states added to CPU instruction fetch; 10-year data retention guarantees integrity across multi-year depot maintenance cycles without battery backup. |
Use Scenario: Captures sensor fusion outputs and GPS timestamps in unmanned aerial vehicle (UAV) flight control units during extended missions. IC Role / Device Role / Timing Role: Page-write buffer for burst-mode logging; leverages 3 ms page write to capture 64 samples before next sensor acquisition window. Use Value: Hardware write protection prevents corruption during engine vibration-induced power glitches; –55°C to +125°C rating sustains operation inside unheated wing-mounted pods. |
| Weapons System Calibration Store | Tactical Radio Configuration |
|
Use Scenario: Holds weapon alignment offsets, laser rangefinder compensation tables, and fuse timing parameters in guided munition guidance sections. IC Role / Device Role / Timing Role: Secure, tamper-resistant configuration store accessed only during pre-launch initialization; SDP enabled after final calibration. Use Value: 10,000-cycle endurance exceeds expected field recalibration frequency; extra 64-byte ID area encodes lot traceability per DFARS 252.211-7003 requirements. |
Use Scenario: Stores cryptographic key slots, frequency hopping sequences, and user-defined channel maps in handheld SINCGARS radios. IC Role / Device Role / Timing Role: Low-power configuration manager; enters <300 µA CMOS standby mode between radio channel changes to extend battery life. Use Value: JEDEC pinout ensures drop-in replacement of legacy 27C256 EPROMs in existing PCBs; 5 V tolerance simplifies integration with discrete transistor-level interface circuits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC256-12DM/883 | 120 ns read access time; 10 ms page write cycle; same endurance and temperature range. | Suitable for cost-sensitive ground-based test equipment where timing margin allows slower access. | Select when system timing budget permits >90 ns latency and longer firmware update windows are acceptable. |
| DS2502-E48+T&R | 1-Wire serial interface; 1024-bit EEPROM; industrial temp (–40°C to +85°C); no page write or polling. | Used in asset tracking tags and simple sensor nodes where pin count and board space are constrained. | Choose only for new designs prioritizing minimal interconnect; not a functional or pinout substitute for AT28HC256F-90DM/883. |
Compared with AT28HC256-12DM/883, the AT28HC256F-90DM/883 delivers 33% faster read access and 3× faster page writes-critical for real-time avionics response. Versus DS2502-E48+T&R, it offers parallel bandwidth, military temperature compliance, and deterministic write signaling absent in 1-Wire protocols.
Availability
AT28HC256F-90DM/883 is available at Aetrix Electronics and suitable for avionics boot memory, mission data loggers, weapons calibration stores, and tactical radio configuration requiring stable component supply under MIL-PRF-38535 Class B sourcing.
Supply support for AT28HC256F-90DM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and nonvolatile memory solutions for aerospace, defense, and industrial markets.
The AT28HC256 product line was developed to deliver radiation-tolerant, high-reliability parallel EEPROMs for legacy 5 V system upgrades and MIL-STD-1553 bus controllers requiring deterministic, page-optimized nonvolatile storage.
FAQ
What is the guaranteed minimum endurance rating for AT28HC256F-90DM/883?
The AT28HC256F-90DM/883 is rated for 10,000 write/erase cycles per memory location under full military temperature conditions (–55°C to +125°C). This endurance is validated per MIL-STD-883 Method 1008 and applies to both byte and page write operations. The device also supports optional extended endurance (100,000 cycles) in non-military variants, but AT28HC256F-90DM/883 specifically guarantees 10,000 cycles.
Does AT28HC256F-90DM/883 require external high-voltage programming circuitry?
No, AT28HC256F-90DM/883 operates from a single 5 V ±10% supply and requires no external high-voltage programming signals. All write and erase functions-including software chip erase-are executed using standard 5 V logic levels. The optional 12 V signal on A9 is used exclusively for accessing the 64-byte device identification area, not for main array programming.
How is write completion detected on AT28HC256F-90DM/883?
AT28HC256F-90DM/883 supports two hardware-confirmed methods: DATA Polling on I/O7 (complement of last written byte appears until write completes) and Toggle Bit on I/O6 (toggles between 0 and 1 during write, then stabilizes). Both methods are valid at any point during the write cycle and eliminate reliance on fixed delays or external timers.
Which packages are available for AT28HC256F-90DM/883?
AT28HC256F-90DM/883 is offered in four hermetically sealed military packages: 32-lead CERDIP (MIL-STD-1835 D-10), 32-lead CLCC (MIL-STD-1835 C-12), 32-lead FLATPACK (MIL-STD-1835 F-12), and 30-pin PGA (MIL-STD-1835 U-12). All share identical pin functions and electrical specifications; mechanical drawings and marking formats are documented in Microchip DS20006352A.
Is software data protection (SDP) enabled by default on AT28HC256F-90DM/883?
No, AT28HC256F-90DM/883 ships with software data protection disabled. SDP must be explicitly enabled using the three-byte command sequence (AAh to 5555h, 55h to 2AAAh, A0h to 5555h). Once enabled, SDP remains active through power cycles and requires the disable sequence (AAh/55h/80h/AAh/20h/55h/2AAAh) to deactivate. The AT28HC256F-90DM/883 supports full SDP functionality per datasheet Section 6.11–6.12.
AT28HC256F-90DM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-CDIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-CerDip
AT28HC256F-90DM/883 FAQ
1.How can I place an order for AT28HC256F-90DM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256F-90DM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256F-90DM/883 reliable?
The price and inventory of AT28HC256F-90DM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256F-90DM/883 is usually 5 days.
3.What payment methods are accepted for AT28HC256F-90DM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256F-90DM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256F-90DM/883?
AT28HC256F-90DM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256F-90DM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256F-90DM/883?
For technical support, including AT28HC256F-90DM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256F-90DM/883 requirements.
6.How does Aetrix verify that AT28HC256F-90DM/883 is sourced from the original manufacturer or authorized distributors?
All AT28HC256F-90DM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256F-90DM/883 meets industry standards.
7.What is the process for return or replacement of AT28HC256F-90DM/883?
All AT28HC256F-90DM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256F-90DM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256F-90DM/883 part is unused and in its original packaging.
Return procedure for AT28HC256F-90DM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256F-90DM/883 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

