My Inquiry
My Account
Microchip Technology AT28HC256F-90JU
- Part No.:
- AT28HC256F-90JU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28HC256F-90JU.pdf
- Description:
- IC EEPROM 256KBIT PAR 32PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:2,344
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256F-90JU from Microchip Technology is a 256-Kbit (32,768 × 8) parallel EEPROM with 90 ns read access time, 3 ms fast page write cycle, single 5V ±10% supply, industrial temperature range (–40°C to +85°C), and JEDEC-approved byte-wide pinout. It serves as nonvolatile program/data storage in microcontroller-based systems requiring reliable reprogrammability without external high-voltage circuitry.
For engineers reviewing the AT28HC256F-90JU datasheet, AT28HC256F-90JU pinout, AT28HC256F-90JU application, or AT28HC256F-90JU equivalent, this page delivers verified electrical specs, JEDEC-compliant package mapping, page-write timing behavior, hardware/software data protection implementation, and real-world use context for embedded firmware storage, configuration retention, and calibration data logging.
Technical Context
The AT28HC256F-90JU implements a CMOS-based parallel EEPROM architecture with internal 64-byte page latches and autonomous control timer for self-timed writes. Its dual-line chip enable (CE) and output enable (OE) logic enables bus contention avoidance in shared-memory systems, while DATA Polling on I/O7 and Toggle Bit on I/O6 provide deterministic end-of-write detection without polling overhead.
It supports both byte and page write modes under identical 5V supply conditions, with hardware write inhibition triggered by VCC < 3.8V, power-on delay (~5 ms), noise filtering (<15 ns pulses rejected), and active-level control logic. The device includes 64 bytes of dedicated identification memory accessible via A9 = 12V and addresses 7FC0H–7FFFH.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 256 Kbit (32,768 × 8) - supports full 16-bit address space with byte-level random access |
| Read Access Time | 90 ns max - enables direct interface with 8/16-bit microcontrollers operating up to ~11 MHz bus frequency |
| Page Write Cycle Time | 3 ms max - reduces firmware update latency vs. standard 10 ms variant (AT28HC256-90) |
| Supply Voltage | 5V ±10% - eliminates need for external voltage regulation in legacy 5V system designs |
| Endurance | 10,000 write cycles - validated for repeated field-upgrade scenarios in industrial controllers |
| Data Retention | 10 years at +85°C - ensures long-term calibration and configuration integrity in unattended equipment |
| Operating Temperature | –40°C to +85°C - qualified for deployment in industrial automation, metering, and automotive body electronics |
| Power Dissipation | 440 mW active, <3 mA standby - compatible with thermally constrained PCB layouts and low-quiescent-power systems |
Pinout & Package
AT28HC256F-90JU is packaged in a 32-lead PLCC (Plastic Leaded Chip Carrier) with JEDEC-standard byte-wide pinout. Pin 1 and Pin 17 are designated "Don't Connect" per datasheet; Pins labeled "DC" and "NC" must remain unconnected in layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path; I/O7 used for DATA Polling, I/O6 for Toggle Bit status indication during writes |
| CE | Chip Enable | Active-low chip select; must be low for read/write access; high-Z output when asserted high |
| OE | Output Enable | Active-low output gate; controls data bus drive; enables bus sharing with other peripherals |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; initiates byte or page programming sequence |
| VCC | Power Supply | +5V ±10% main supply; powers core logic and I/O buffers; internal VCC sense prevents writes below 3.8V |
| GND | Ground Reference | Signal and power return path; requires low-impedance connection to minimize noise coupling during write operations |
| DC, NC | No Connect / Don't Connect | Pins 1, 12, 17, 26 - must be left floating; no internal connection or function |
Key Features
| Feature | Design Value |
|---|---|
| Fast 3 ms Page Write | Reduces firmware update time by 70% vs. 10 ms standard variant-critical for factory programming throughput and field OTA updates |
| Hardware Write Inhibition | Prevents corruption during brown-out or power ramp-up via VCC sensing and 5 ms power-on delay-no external supervisor IC required |
| DATA Polling & Toggle Bit | Enables deterministic, zero-overhead write completion detection using only I/O7 or I/O6-eliminates fixed-delay wait states in host firmware |
| Software Data Protection (SDP) | Configurable lock/unlock via 3-byte command sequence (AAh/55h/A0h enable; AAh/55h/80h/AAh/20h/55h disable)-prevents accidental writes in deployed systems |
| Dedicated ID Memory | 64 bytes accessible at 7FC0H–7FFFH with A9 = 12V-enables unique device serialization, calibration traceability, and revision tracking |
| JEDEC Byte-Wide Pinout | Direct drop-in compatibility with industry-standard SRAM and EPROM sockets-simplifies board reuse and legacy design migration |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Retention |
|---|---|
Use Scenario: Storing user-configurable I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via parallel bus during boot and runtime parameter updates. Use Value: Ensures settings survive power loss and retain accuracy over 10-year service life at 85°C ambient-meeting IEC 61131-3 reliability requirements. | Use Scenario: Holding factory-calibrated sensor offsets, gain coefficients, and safety-critical operational limits in portable diagnostic equipment. IC Role / Device Role / Timing Role: Secure, tamper-resistant data vault with software protection enabled to prevent unauthorized parameter modification. Use Value: Guarantees traceable calibration validity across device lifetime, satisfying FDA 21 CFR Part 11 electronic record integrity mandates. |
| Automotive Body Control Module (BCM) Settings | Test Equipment Firmware Patch Storage |
Use Scenario: Persisting seat/mirror position presets, lighting profiles, and door lock behavior in 12V automotive BCMs exposed to thermal cycling. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to 8-bit MCU without glue logic-supports rapid recall of user preferences at ignition-on. Use Value: Delivers 90 ns read access and –40°C to +85°C operation-ensuring sub-100 ms UI response and AEC-Q100 Grade 2 compliance. | Use Scenario: Hosting field-upgradable test algorithm binaries and measurement compensation tables in automated bench instruments. IC Role / Device Role / Timing Role: High-reliability firmware repository enabling in-situ patching without instrument downtime or rework. Use Value: 3 ms page write cuts patch deployment time by >65% vs. standard EEPROMs-increasing test lab utilization and reducing calibration cycle time. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC256-90JU | 10 ms page write cycle; same 90 ns read speed, 5V supply, and PLCC-32 package | Lacks fast 3 ms write capability-suitable where update frequency is low and cost sensitivity is higher | Select when firmware update latency is non-critical and BOM cost optimization is prioritized over programming speed |
| ST M28W256FCT | 256 Kbit parallel EEPROM with 100 ns access, 5V supply, but requires separate 12V for chip erase; different pinout (28-SOIC) | No integrated software data protection; lacks dedicated ID memory; not JEDEC byte-pinout compatible | Choose only if existing 28-SOIC footprint and 12V availability exist-requires PCB redesign and firmware adaptation for erase/protection logic |
Compared with AT28HC256-90JU, the AT28HC256F-90JU delivers 70% faster page writes without changing voltage, timing, or interface-making it optimal for high-volume programming or frequent field updates. Versus ST M28W256FCT, it offers plug-compatible JEDEC pinout, integrated SDP, and no external high-voltage requirement-reducing system complexity and qualification risk.
Availability
AT28HC256F-90JU is available at Aetrix Electronics and suitable for industrial automation, medical diagnostics, and automotive body electronics requiring stable component supply, long-lifecycle support, and guaranteed green (RoHS-compliant) packaging.
Supply support for AT28HC256F-90JU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions, with a focus on embedded control and connectivity.
The AT28HC256 product line delivers high-speed, industrial-grade parallel EEPROMs designed for firmware storage, configuration retention, and calibration data logging in resource-constrained 5V systems.
FAQ
What is the maximum page write cycle time for AT28HC256F-90JU?
The AT28HC256F-90JU has a maximum page write cycle time of 3 ms, as confirmed in Section 6.8 of the official Microchip datasheet DS20006428B. This is a key differentiator from the standard AT28HC256-90JU (10 ms), achieved through optimized internal timing without requiring changes to VCC, interface signals, or host firmware timing margins. The 3 ms specification applies across the full industrial temperature range.
Does AT28HC256F-90JU support both hardware and software data protection?
Yes, AT28HC256F-90JU implements dual-layer protection: hardware features include VCC sensing (<3.8V inhibit), 5 ms power-on delay, noise filtering (<15 ns pulse rejection), and CE/OE/WE level monitoring; software data protection (SDP) is enabled/disabled via documented 3-byte command sequences (AAh/55h/A0h and AAh/55h/80h/AAh/20h/55h). Both mechanisms operate independently and are fully functional in the AT28HC256F-90JU.
What package type and pin count does AT28HC256F-90JU use?
AT28HC256F-90JU uses a 32-lead Plastic Leaded Chip Carrier (PLCC) package, as indicated by the "JU" suffix per Microchip's marking convention (DS20006428B, Section 7.1). Pin 1 and Pin 17 are designated "Don't Connect" (DC); Pins 12 and 26 are "No Connect" (NC). The device adheres to JEDEC-approved byte-wide pinout, enabling direct replacement of legacy SRAM and EPROM devices.
How is end-of-write detection implemented in AT28HC256F-90JU?
AT28HC256F-90JU provides two independent, hardware-verified methods: DATA Polling monitors complemented data on I/O7 during write cycles, returning true data once complete; Toggle Bit observes state transitions on I/O6, which cease toggling upon write completion. Both methods are characterized across temperature and voltage per Tables 6-5 and 6-6 in DS20006428B and require no external components or timing assumptions.
Is AT28HC256F-90JU RoHS-compliant and what is its endurance rating?
Yes, AT28HC256F-90JU is RoHS-compliant ("Green Packaging Option Only", DS20006428B, Feature list) and rated for 10,000 write/erase cycles with 10-year data retention at +85°C. These values are measured and guaranteed per Microchip's qualification testing (Section 3, "High Reliability CMOS Technology") and apply identically to the F-suffix fast-write variant-no derating is required for the 3 ms page write mode.
AT28HC256F-90JU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28HC256F-90JU FAQ
1.How can I place an order for AT28HC256F-90JU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256F-90JU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256F-90JU reliable?
The price and inventory of AT28HC256F-90JU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256F-90JU is usually 5 days.
3.What payment methods are accepted for AT28HC256F-90JU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256F-90JU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256F-90JU?
AT28HC256F-90JU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256F-90JU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256F-90JU?
For technical support, including AT28HC256F-90JU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256F-90JU requirements.
6.How does Aetrix verify that AT28HC256F-90JU is sourced from the original manufacturer or authorized distributors?
All AT28HC256F-90JU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256F-90JU meets industry standards.
7.What is the process for return or replacement of AT28HC256F-90JU?
All AT28HC256F-90JU units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256F-90JU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256F-90JU part is unused and in its original packaging.
Return procedure for AT28HC256F-90JU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256F-90JU Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
