Microchip Technology AT28HC256F-90JU-T

Overview

AT28HC256F-90JU-T from Microchip Technology is a 256-Kbit (32,768 × 8) parallel EEPROM with 90 ns read access time, 3 ms page write cycle, industrial temperature range (−40°C to +85°C), and single 5V ±10% supply. It operates as a byte-wide nonvolatile memory in embedded control systems requiring reliable firmware storage and configuration retention.

For engineers reviewing the AT28HC256F-90JU-T datasheet, AT28HC256F-90JU-T pinout, AT28HC256F-90JU-T application, or AT28HC256F-90JU-T equivalent, key selection criteria include JEDEC-compliant 28-pin SOIC package, hardware/software data protection, DATA Polling and Toggle Bit write completion detection, and fast 3 ms page write capability for field-upgradable systems.

Technical Context

The AT28HC256F-90JU-T implements a CMOS-based parallel EEPROM architecture with internal 64-byte page latching, automatic internal write timing, and dual-line chip/enable control (CE/OE) for bus contention avoidance. Its block diagram includes Y/X decoders, input/output buffers, and dedicated logic for WE/CE/OE state decoding.

It supports three primary operational modes: Read (CE=low, OE=low, WE=high), Byte Write (CE=low, OE=high, WE=low), and Page Write (up to 64 bytes within same A6–A14 page boundary). Write completion is verified via I/O7 DATA Polling or I/O6 Toggle Bit, both usable at any point during tWC.

Key Specifications

Pinout & Package

AT28HC256F-90JU-T is packaged in a 28-lead Small Outline Integrated Circuit (SOIC) with JEDEC-standard byte-wide pinout. The package is RoHS-compliant, green, and surface-mountable with 1.27 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28HC256-90JU, the AT28HC256F-90JU-T delivers 70% faster page writes for rapid field updates, while M95256-DW offers serial interface savings at the cost of bus arbitration complexity and loss of direct memory-mapped access.

Availability

AT28HC256F-90JU-T is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, smart metering systems, and automotive body control modules requiring stable component supply across multi-year production cycles.

Supply support for AT28HC256F-90JU-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions with a focus on industrial, automotive, and aerospace reliability standards.

The AT28HC256 product line delivers high-speed parallel EEPROMs optimized for embedded systems needing direct bus interface, fast write performance, and robust data integrity under harsh electrical and thermal conditions.

FAQ

What is the maximum page write size supported by the AT28HC256F-90JU-T?

The AT28HC256F-90JU-T supports up to 64 bytes per page write operation. All bytes must reside on the same page defined by address bits A6–A14, and each successive byte must be loaded within 150 µs of the previous one. This capability is confirmed in Section 6.8 of the DS20006428B datasheet and distinguishes the "F" variant with its 3 ms maximum write cycle time. The AT28HC256F-90JU-T uses internal latching to free the address/data bus during programming.

Does the AT28HC256F-90JU-T require external high-voltage circuitry for write operations?

No, the AT28HC256F-90JU-T performs all write operations using only the standard 5 V ±10% supply. Unlike older EPROMs, it does not require 12 V or other elevated voltages for programming. Chip erase and software protection commands also execute at 5 V. The 12 V specification referenced in the datasheet applies exclusively to optional device identification memory access (A9 = 12 V), not to normal read/write functions of the AT28HC256F-90JU-T.

How does hardware write protection work on the AT28HC256F-90JU-T?

Hardware write protection on the AT28HC256F-90JU-T operates through four mechanisms: (1) VCC sense circuitry inhibits writes if supply drops below ~3.8 V; (2) a 5 ms internal power-on delay prevents writes until VCC stabilizes; (3) write is blocked unless CE is low, OE is high, and WE is low simultaneously; and (4) a noise filter rejects sub-15 ns pulses on CE/WE. These features are active by default and require no configuration, ensuring robustness against power glitches and EMI in industrial environments containing the AT28HC256F-90JU-T.

Can the AT28HC256F-90JU-T be used as a direct replacement for standard SRAM in existing designs?

Yes, the AT28HC256F-90JU-T is designed for SRAM-like read access - CE and OE low with WE high enables direct read without external timing logic. However, write cycles differ: it requires controlled WE strobing and supports page writes, unlike volatile SRAM. Its JEDEC byte-wide pinout matches many SRAM footprints, but designers must implement write completion detection (via DATA Polling or Toggle Bit) and ensure proper CE/OE/WE sequencing. The AT28HC256F-90JU-T is not a functional drop-in for SRAM in write-intensive applications due to endurance limits.

What is the purpose of the extra 64 bytes of EEPROM in the AT28HC256F-90JU-T?

The AT28HC256F-90JU-T includes 64 bytes of dedicated identification memory accessible at addresses 7FC0H–7FFFH when A9 is raised to 12 V ±0.5 V. This area is intended for storing unique device identifiers, calibration data, manufacturing lot codes, or firmware version stamps. It operates independently of the main 256-Kbit array and retains data for 10 years. Use requires applying 12 V to A9 - a feature not needed for standard operation of the AT28HC256F-90JU-T but valuable for traceability in regulated industries.