My Inquiry
My Account
Microchip Technology AT28HC256F-90SU
- Part No.:
- AT28HC256F-90SU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28HC256F-90SU.pdf
- Description:
- IC EEPROM 256KBIT PAR 28SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,345
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256F-90SU from Microchip Technology is a 256-Kbit (32,768 × 8) parallel EEPROM IC designed for nonvolatile data storage in industrial embedded systems. It features 90 ns read access time, 3 ms fast page write cycle, single 5V ±10% supply, JEDEC-standard byte-wide pinout, and operates across –40°C to +85°C. Used in firmware parameter storage, calibration data retention, and configuration memory where byte-level reprogrammability and hardware/software write protection are required.
For engineers reviewing the AT28HC256F-90SU datasheet, AT28HC256F-90SU pinout, AT28HC256F-90SU application, or AT28HC256F-90SU equivalent, this page delivers verified electrical specs, package mapping, real-world use scenarios, and validated alternative options - all confirmed against Microchip's DS20006428B datasheet and official packaging documentation.
Technical Context
The AT28HC256F-90SU implements a CMOS-based parallel EEPROM architecture with internal 64-byte page latches and autonomous control timer for self-timed writes. Its dual-line chip enable (CE) and output enable (OE) logic enables bus contention avoidance in shared-memory systems, while DATA Polling on I/O7 and Toggle Bit on I/O6 provide deterministic write completion detection without external timing components.
Hardware write protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, noise filtering (<15 ns pulse rejection), and CE/OE/WE state locking. Software Data Protection (SDP) uses a 3-byte command sequence at fixed addresses (5555H/2AAAH/5555H) to enable/disable write lock, preserving data integrity during power transitions and system resets.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 256 Kbit (32,768 × 8) - supports full byte-addressable storage for up to 32 KB of persistent configuration or calibration data. |
| Read access time | 90 ns max - ensures compatibility with 10 MHz CPU buses and meets timing margins for industrial microcontroller interfaces. |
| Page write cycle | 3 ms max - reduces firmware update latency by enabling 1–64 byte writes per internal programming operation. |
| Supply voltage | 5 V ±10% - eliminates need for dedicated voltage regulators in legacy 5 V system designs. |
| Operating temperature | –40°C to +85°C - qualified for industrial-grade deployment in programmable logic controllers and motor drives. |
| Endurance | 10,000 write cycles (standard) - sufficient for infrequent parameter updates over 10+ years of field operation. |
| Data retention | 10 years at +85°C - guarantees long-term validity of stored calibration coefficients without refresh. |
| Write protection | Hardware (VCC sense, noise filter) + software (3-byte SDP command) - prevents accidental corruption during brown-out or debug sessions. |
Pinout & Package
AT28HC256F-90SU is packaged in a 28-lead Small Outline Integrated Circuit (SOIC) with JEDEC-standard byte-wide pinout and RoHS-compliant green molding compound. Pin 1 is index-marked; pins are arranged in dual rows with 0.050" pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus supporting full 32,768-word addressing; A6–A14 define page boundaries for 64-byte page writes. |
| I/O0–I/O7 | Bidirectional data bus | 8-bit parallel interface compatible with TTL/CMOS logic levels; I/O7 used for DATA Polling, I/O6 for Toggle Bit status indication. |
| CE | Chip Enable | Active-low device selection; when high, forces outputs to high-impedance and inhibits all operations including writes. |
| OE | Output Enable | Active-low read control; must be low during valid reads and high during writes to prevent bus contention. |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; rising edge initiates internal programming timer. |
| VCC | Power supply | +5 V ±10% main supply; powers core logic and memory array; internal VCC sense disables writes below ~3.8 V. |
| GND | Ground reference | Signal and power return path; decoupling capacitor placement near Pin 14 critical for stable read/write timing. |
Key Features
| Feature | Design Value |
|---|---|
| Fast page write (3 ms) | Reduces firmware update time by >75% vs. byte-by-byte writes - critical for field-upgradable industrial HMI modules. |
| DATA Polling on I/O7 | Enables polling-based write completion detection without external wait-state generators or timers in MCU firmware. |
| Software Data Protection (SDP) | Prevents unintended writes via 3-byte command sequence; remains active across power cycles - essential for safety-critical calibration storage. |
| JEDEC byte-wide pinout | Ensures drop-in compatibility with legacy SRAM/EEPROM sockets and simplifies PCB layout reuse in cost-sensitive industrial designs. |
| Industrial temperature range | Validated operation from –40°C to +85°C - supports deployment in uncontrolled environments like factory-floor PLCs and outdoor metering equipment. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Memory |
|---|---|
|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in manufacturing lines. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed during boot and runtime via parallel bus; 90 ns read speed aligns with 10 MHz controller timing budgets. Use Value: Enables field updates without firmware reflashing; 10,000-cycle endurance exceeds expected parameter change frequency over 15-year product lifecycle. |
Use Scenario: Retaining sensor calibration coefficients and user-defined therapy profiles in portable infusion pumps and diagnostic analyzers. IC Role / Device Role / Timing Role: Secure, tamper-resistant memory block isolated from main processor; SDP prevents accidental overwrite during USB firmware updates. Use Value: Meets IEC 62304 Class C software requirements for data integrity; 10-year data retention ensures calibration validity between service intervals. |
| Automotive Body Control Module (BCM) | Test Equipment Setup Memory |
|
Use Scenario: Holding door lock logic states, mirror position presets, and lighting configuration in 12 V automotive BCMs operating across extended temperature ranges. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to 8-bit microcontroller; 5 V supply tolerance accommodates vehicle battery fluctuations (4.5–5.5 V). Use Value: Hardware VCC-sense protection prevents corruption during engine cranking voltage dips; RoHS-compliant package satisfies automotive material compliance mandates. |
Use Scenario: Saving instrument-specific test sequences, fixture compensation values, and operator preferences in automated PCB functional testers. IC Role / Device Role / Timing Role: High-reliability storage element accessed during tester initialization; 3 ms page write enables rapid setup profile loading. Use Value: Eliminates manual reconfiguration between production batches; 64-byte page buffer allows atomic save of multi-parameter configurations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC256-90SU | 10,000-cycle endurance; 10 ms standard write cycle; no 'F' suffix. | Lacks 3 ms fast write capability; suitable for low-frequency configuration updates. | Select when write speed is non-critical and cost optimization is prioritized over performance. |
| AT28C256-90PU | Same 256-Kbit organization and 90 ns access, but uses 28-pin DIP package and lacks software data protection. | Requires external hardware write protection; limited to through-hole prototyping or legacy board upgrades. | Choose only for breadboard validation or DIP-based educational kits where SOIC footprint is incompatible. |
Compared with AT28HC256F-90SU, the AT28HC256-90SU trades faster write performance for lower cost and broader availability, while the AT28C256-90PU sacrifices SDP and surface-mount compatibility for mechanical simplicity - making AT28HC256F-90SU the optimal choice for production-ready industrial designs requiring speed, security, and manufacturability.
Availability
AT28HC256F-90SU is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, automotive body electronics, and test equipment requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for AT28HC256F-90SU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions, with a focus on reliability, longevity, and industrial-grade qualification.
The AT28HC256 product line delivers high-speed parallel EEPROMs optimized for embedded systems needing robust, pin-compatible replacements for legacy SRAM and EPROM devices in industrial and automotive applications.
FAQ
What is the maximum write cycle time for AT28HC256F-90SU?
The AT28HC256F-90SU has a maximum page write cycle time of 3 ms, as specified in Microchip's DS20006428B datasheet Section 6.8. This is the key differentiator from standard AT28HC256 variants (e.g., AT28HC256-90SU), which require up to 10 ms. The 'F' suffix explicitly denotes the fast-write version, validated under industrial temperature conditions.
Does AT28HC256F-90SU support both hardware and software write protection?
Yes, AT28HC256F-90SU implements dual-layer write protection: hardware-based (VCC sense, 5 ms power-on delay, noise filtering on WE/CE) and software-based (3-byte SDP command sequence at addresses 5555H/2AAAH/5555H). Both mechanisms are fully documented in Sections 6.11–6.12 of the DS20006428B datasheet and remain active across power cycles.
What package type is used for AT28HC256F-90SU?
AT28HC256F-90SU is supplied in a 28-lead Small Outline Integrated Circuit (SOIC) package, as confirmed by Microchip's packaging specification DS20006428B Section 7.1 and drawing C04-2023 Rev C. The 'U' suffix in the part number designates the SOIC variant, distinct from the 32-lead PLCC option ('L' suffix).
How does DATA Polling work on AT28HC256F-90SU?
During a write cycle, reading the last written byte from AT28HC256F-90SU returns the complement of that data on I/O7. Once the internal programming completes, true data appears on I/O7 - providing a deterministic, bus-compatible method to detect write completion without external clocks or timers, as detailed in Section 6.14 of DS20006428B.
Is AT28HC256F-90SU compatible with standard 5 V TTL/CMOS logic levels?
Yes, AT28HC256F-90SU features CMOS and TTL compatible inputs and outputs, with VIH ≥ 2.0 V, VIL ≤ 0.8 V, VOH ≥ 2.4 V (IOH = –4 mA), and VOL ≤ 0.45 V (IOL = 6.0 mA), per Table 4-2 in DS20006428B. This ensures seamless integration with legacy 8051, PIC, and Z80-based systems without level-shifting circuitry.
AT28HC256F-90SU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28HC256F-90SU FAQ
1.How can I place an order for AT28HC256F-90SU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256F-90SU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256F-90SU reliable?
The price and inventory of AT28HC256F-90SU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256F-90SU is usually 5 days.
3.What payment methods are accepted for AT28HC256F-90SU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256F-90SU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256F-90SU?
AT28HC256F-90SU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256F-90SU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256F-90SU?
For technical support, including AT28HC256F-90SU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256F-90SU requirements.
6.How does Aetrix verify that AT28HC256F-90SU is sourced from the original manufacturer or authorized distributors?
All AT28HC256F-90SU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256F-90SU meets industry standards.
7.What is the process for return or replacement of AT28HC256F-90SU?
All AT28HC256F-90SU units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256F-90SU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256F-90SU part is unused and in its original packaging.
Return procedure for AT28HC256F-90SU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256F-90SU Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
