Microchip Technology AT28HC256F-90TU-T
- Part No.:
- AT28HC256F-90TU-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-TSSOP (0.465", 11.80mm Width)
- Datasheet:
-
AT28HC256F-90TU-T.pdf
- Description:
- IC EEPROM 256KBIT PAR 28TSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,299
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256F-90TU-T from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 90 ns read access time, 3 ms maximum page write cycle time, and full operation across –55°C to +125°C. It supports hardware/software data protection, DATA polling for write completion detection, and operates from a single 5V ±10% supply in systems requiring nonvolatile memory with high reliability and fast page writes.
For engineers reviewing the AT28HC256F-90TU-T datasheet, AT28HC256F-90TU-T pinout, AT28HC256F-90TU-T application, or AT28HC256F-90TU-T equivalent, this device serves as a drop-in replacement for legacy 28-pin/32-pin parallel EEPROMs in avionics, defense computing, and space-qualified embedded controllers where extended endurance (10,000 cycles), 10-year data retention, and JEDEC byte-wide pin compatibility are required.
Technical Context
The AT28HC256F-90TU-T implements a paged architecture with an internal 64-byte latch enabling simultaneous write of 1–64 bytes per cycle. Its control logic uses CE/OE/WE three-line protocol for SRAM-like read/write timing without external circuitry.
It integrates VCC sense (write inhibit below 3.8 V), 5 ms power-on delay, noise filtering on WE/CE (<15 ns pulses rejected), and optional software data protection via 3-byte unlock sequence (AAh/55h/A0h) - all active across the full military temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32,768 × 8) - provides full byte-addressable nonvolatile storage for firmware boot code or configuration tables |
| Read Access Time | 90 ns - enables direct interface with 10 MHz+ microcontrollers without wait states |
| Page Write Cycle Time | 3 ms max - reduces firmware update latency vs. byte-write-only EEPROMs |
| Endurance | 10,000 write/erase cycles - validated for mission-critical field updates in sealed systems |
| Data Retention | 10 years at +125°C - meets MIL-STD-883 requirement for long-term unpowered storage |
| Supply Voltage | 5V ±10% - compatible with legacy TTL/CMOS bus interfaces without level shifters |
| Operating Temperature | –55°C to +125°C - qualified per MIL-PRF-38535 Class B for flight-critical applications |
Pinout & Package
AT28HC256F-90TU-T is supplied in a 32-lead CLCC (Ceramic Leadless Chip Carrier) package with 1.02 mm lead pitch, hermetically sealed for high-reliability environments. Pin 1 is marked by index corner; pins 1 and 17 are "Don't Connect" (DC).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional Data Bus | CMOS/TTL-compatible 8-bit data path; I/O7 used for DATA polling, I/O6 for toggle-bit status |
| CE | Chip Enable | Active-low chip select; must be low for read/write; high-Z output when high |
| OE | Output Enable | Active-low output gate; controls data bus drive during reads; high-Z when high |
| WE | Write Enable | Active-low write strobe; latches address/data on falling edge; initiates byte or page write |
| VCC | Power Supply | +5V ±10% main supply; internal VCC sense disables writes if voltage drops below 3.8 V |
| GND | Ground Reference | Signal and power ground reference; decoupling required within 10 mm of VCC pin |
| NC / DC | No Connect / Don't Connect | Pins 1 and 17 - must remain unconnected; no internal connection or function |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte internal page register | Enables burst programming of up to 64 bytes without re-latching address, reducing host CPU overhead by >90% vs. byte-by-byte writes |
| DATA Polling on I/O7 | Allows real-time detection of write completion without timers or interrupts - critical for deterministic boot sequences |
| Software Data Protection (SDP) | Prevents accidental writes via 3-byte unlock sequence (AAh/55h/A0h); remains active through power cycles |
| Hardware write inhibit | Combines VCC sensing, 5 ms power-on delay, and noise filtering to eliminate false writes during brown-out or EMI events |
| Extra 64-byte ID area | Accessible at 7FC0h–7FFFh with A9 = 12 V; used for serialization, calibration data, or firmware version tracking |
Applications
| Avionics Flight Control Unit | Military Radio Firmware Storage |
|---|---|
Use Scenario: Storing real-time sensor calibration coefficients and flight envelope limits in a triple-modular-redundant (TMR) flight computer. IC Role / Device Role / Timing Role: Nonvolatile configuration memory providing deterministic read access <90 ns during control loop execution. Use Value: Ensures consistent parameter loading across power cycles and radiation-induced resets without external refresh circuitry. | Use Scenario: Holding encrypted firmware images and cryptographic keys in a Type 1 COMSEC radio operating in harsh RF environments. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage with hardware/software write protection preventing unauthorized firmware modification. Use Value: Meets NSA-certified secure boot requirements by isolating key material from volatile RAM and blocking unintended writes during ESD transients. |
| Satellite Onboard Computer | Tactical Vehicle Diagnostic Module |
Use Scenario: Saving telemetry history and fault logs in a radiation-hardened OBC where memory must survive 10+ years in orbit. IC Role / Device Role / Timing Role: Long-retention data logger using 10-year guaranteed data hold at +125°C and 10,000-cycle endurance. Use Value: Eliminates need for periodic ground-based data dump and rewrite, reducing downlink bandwidth and mission risk. | Use Scenario: Recording engine diagnostics and CAN bus error counters in armored vehicle ECUs exposed to wide thermal cycling. IC Role / Device Role / Timing Role: High-reliability event recorder interfacing directly to 5V microcontroller buses without level translation. Use Value: Maintains data integrity across –55°C cold starts and +125°C under-hood operation without backup batteries or capacitors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC256-90JU | Same die, 32-lead CERDIP package; 10 ms max page write time; 10,000-cycle endurance | Used in legacy board designs with through-hole mounting; lacks CLCC's thermal performance and hermetic seal | Select when retrofitting existing CERDIP footprints or when cost sensitivity outweighs speed/reliability needs |
| DS2502-E48+ | 1-Wire serial EEPROM; 48-bit laser-programmed ID; no parallel bus; 100K endurance | Designed for asset tagging and simple parameter storage; incompatible pinout and protocol | Choose only for new designs prioritizing minimal pin count over speed, where 1-Wire infrastructure already exists |
Compared with AT28HC256-90JU, the AT28HC256F-90TU-T delivers 3× faster page writes and superior thermal stability in CLCC packaging; versus DS2502-E48+, it provides full parallel bus throughput and deterministic timing but requires more PCB real estate and power.
Availability
AT28HC256F-90TU-T is available at Aetrix Electronics and suitable for avionics, defense electronics, and satellite subsystems requiring stable component supply with full MIL-PRF-38535 traceability and extended temperature qualification.
Supply support for AT28HC256F-90TU-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with a focus on high-reliability and embedded control markets.
The AT28HC256F-90TU-T belongs to Microchip's military-grade parallel EEPROM product line, designed specifically for applications demanding extended temperature operation, high endurance, and robust data integrity in safety-critical systems.
FAQ
What is the maximum page write size supported by the AT28HC256F-90TU-T?
The AT28HC256F-90TU-T supports a maximum page write size of 64 bytes. This is enabled by its internal 64-byte page register, which allows the host to load up to 64 sequential bytes within a 150 µs window (tBLC) before the device automatically initiates the internal programming cycle. Each byte must reside on the same page, defined by address bits A6–A14, and A0–A5 select the specific byte positions within that page. The AT28HC256F-90TU-T achieves this with a maximum page write cycle time of 3 ms.
Does the AT28HC256F-90TU-T require external high-voltage programming signals?
No, the AT28HC256F-90TU-T operates from a single 5V ±10% supply and does not require external high-voltage programming signals for standard byte or page writes. Only the optional chip erase mode (using a 6-byte software command) and device identification area programming require 12.0 V ±0.5 V applied to A9 - all other operations, including DATA polling and software data protection enable/disable, use standard 5V logic levels. The AT28HC256F-90TU-T integrates internal charge pumps and voltage regulation to manage internal programming voltages.
How is write completion detected on the AT28HC256F-90TU-T?
Write completion on the AT28HC256F-90TU-T can be detected using two hardware methods: DATA polling on I/O7 and the toggle bit on I/O6. During a write, reading the last written byte returns the complement of the data on I/O7; when true data appears, the write is complete. Alternatively, I/O6 toggles between 0 and 1 during the write and stops toggling once finished. Both methods allow polling without timers or interrupts. The AT28HC256F-90TU-T guarantees these functions operate across the full –55°C to +125°C range.
What package type is used for the AT28HC256F-90TU-T, and what are its key mechanical features?
The AT28HC256F-90TU-T uses a 32-lead CLCC (Ceramic Leadless Chip Carrier) package with a 1.02 mm lead pitch, hermetically sealed ceramic body, and nickel-iron-cobalt alloy leads. It measures 11.63 mm × 11.23 mm × 2.16 mm (max height), features an index corner for orientation, and has "Don't Connect" pins at positions 1 and 17. This package provides superior thermal conductivity, moisture resistance, and mechanical stability compared to CERDIP or flatpack variants - essential for high-reliability military and aerospace deployments. The AT28HC256F-90TU-T is marked with military date code YQyywwl and endurance grade "F" (10K cycles, 3 ms TWC).
Is the AT28HC256F-90TU-T pin-compatible with standard 28-pin parallel EEPROMs?
No, the AT28HC256F-90TU-T is not pin-compatible with standard 28-pin parallel EEPROMs. It uses a 32-lead CLCC package with JEDEC byte-wide pinout but differs in pin count, physical layout, and pin functions - for example, it includes dedicated DC (Don't Connect) pins and maps A12–A14 to different locations than 28-pin variants like the AT28HC256-90JU. While the logical interface (A0–A14, I/O0–I/O7, CE/OE/WE, VCC/GND) is functionally identical, PCB layout must match the 32-pad CLCC footprint. The AT28HC256F-90TU-T is intended for new designs requiring enhanced thermal and reliability performance, not drop-in replacement of legacy 28-pin packages.
AT28HC256F-90TU-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.465", 11.80mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSOP
AT28HC256F-90TU-T FAQ
1.How can I place an order for AT28HC256F-90TU-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256F-90TU-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256F-90TU-T reliable?
The price and inventory of AT28HC256F-90TU-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256F-90TU-T is usually 5 days.
3.What payment methods are accepted for AT28HC256F-90TU-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256F-90TU-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256F-90TU-T?
AT28HC256F-90TU-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256F-90TU-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256F-90TU-T?
For technical support, including AT28HC256F-90TU-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256F-90TU-T requirements.
6.How does Aetrix verify that AT28HC256F-90TU-T is sourced from the original manufacturer or authorized distributors?
All AT28HC256F-90TU-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256F-90TU-T meets industry standards.
7.What is the process for return or replacement of AT28HC256F-90TU-T?
All AT28HC256F-90TU-T units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256F-90TU-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256F-90TU-T part is unused and in its original packaging.
Return procedure for AT28HC256F-90TU-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256F-90TU-T Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

