Microchip Technology AT28HC256F-90UM/883
- Part No.:
- AT28HC256F-90UM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-BCPGA
- Datasheet:
-
AT28HC256F-90UM/883.pdf
- Description:
- IC EEPROM 256KBIT PAR 28CPGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,609
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC256F-90UM/883 from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 90 ns read access time, 3 ms maximum page write cycle time, and full operation across –55°C to +125°C. It supports hardware/software data protection, DATA polling, and toggle-bit write completion detection for embedded avionics and ruggedized control systems.
For engineers reviewing the AT28HC256F-90UM/883 datasheet, AT28HC256F-90UM/883 pinout, AT28HC256F-90UM/883 application, or AT28HC256F-90UM/883 equivalent, key selection considerations include its MIL-STD-883 qualified 30-pin PGA package, 5V ±10% single-supply operation, JEDEC byte-wide pinout compatibility, and 10,000-cycle endurance with 10-year data retention.
Technical Context
The AT28HC256F-90UM/883 implements a paged architecture with an internal 64-byte latch enabling simultaneous writes of 1–64 bytes per page. Its write timing is governed by an internal control timer, eliminating external timing components during page programming.
It features dual write-detection mechanisms-DATA Polling on I/O7 and toggle-bit behavior on I/O6-and integrates VCC sense, power-on delay, noise filtering, and software data protection (SDP) to prevent inadvertent writes during power transitions or noise events.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 256 Kbit (32,768 × 8), organized as byte-addressable nonvolatile storage |
| Read Access Time | 90 ns maximum - enables direct replacement of SRAM in legacy military bus interfaces without wait-state insertion |
| Page Write Cycle Time | 3 ms maximum - reduces firmware update latency vs. standard 10 ms variants in field-programmable systems |
| Operating Temperature | –55°C to +125°C - qualified per MIL-STD-883 for deployment in airborne, missile, and space-qualified platforms |
| Supply Voltage | 5V ±10% - compatible with legacy TTL/CMOS logic families and eliminates need for auxiliary voltage regulators |
| Endurance & Retention | 10,000 write/erase cycles, 10-year data retention - validated under accelerated life testing per MIL-STD-883 Method 1015 |
| Write Protection | Hardware (VCC sense, 5 ms power-on delay, noise filter) and software (3-byte SDP command sequence) - prevents corruption during brownout or EMI events |
Pinout & Package
AT28HC256F-90UM/883 is supplied in a 30-pin ceramic Pin Grid Array (PGA) package compliant with MIL-STD-1835 U-configuration, featuring hermetic sealing and lead finish suitable for high-reliability solder reflow or socketed deployment.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32,768-word addressing; A6–A14 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional Data Bus | CMOS/TTL-compatible 8-bit data path; I/O7 used for DATA Polling, I/O6 for toggle-bit status indication |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; initiates write when pulsed low with OE high |
| OE | Output Enable | Active-low output control; places I/O pins in high-impedance state when high, preventing bus contention |
| WE | Write Enable | Active-low write strobe; latches address/data on falling edge; controls byte or page write initiation |
| VCC | Power Supply | +5V ±10% supply input; internal VCC sense circuitry inhibits writes below ~3.8V |
| GND | Ground Reference | Signal and power ground reference plane; decoupling required within 10 mm of VCC pin per MIL-STD-883 |
| DC (Pins 1, 17) | Don't Connect | No internal connection; must remain unconnected per CLCC package marking note and pin function table |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte internal page register | Enables burst programming of up to 64 bytes without external address sequencing - reduces host CPU overhead in boot loader or configuration updates |
| DATA Polling on I/O7 | Allows real-time detection of write completion via read-back of complemented data - eliminates need for fixed delays or external timers |
| Toggle-bit status on I/O6 | Provides asynchronous write-status feedback independent of address location - simplifies interrupt-driven firmware design |
| Software Data Protection (SDP) | 3-byte enable/disable command sequence prevents accidental writes without compromising full memory accessibility after authentication |
| Optional 64-byte ID sector | Accessible via A9 = 12V ±0.5V at addresses 7FC0H–7FFFH - supports unique device serialization and calibration data storage |
Applications
| Avionics Flight Control Memory | Military Radar Calibration Storage |
|---|---|
Use Scenario: Storing real-time trim coefficients and fault history in fly-by-wire flight computers operating in extended thermal environments. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced directly to MIL-STD-1553 or discrete bus controllers; replaces battery-backed SRAM. Use Value: Eliminates battery maintenance and failure modes while maintaining 90 ns read performance for deterministic loop timing. | Use Scenario: Holding factory-calibrated RF gain tables and beam-steering parameters in phased-array radar transceivers. IC Role / Device Role / Timing Role: High-reliability parameter store accessed during system initialization and periodic recalibration; operates across full military temperature range. Use Value: Ensures parameter integrity over 10-year service life without refresh, meeting DO-160E Section 22 environmental stress requirements. |
| Tactical Vehicle Engine Control | Spacecraft Onboard Telemetry Logger |
Use Scenario: Recording engine runtime diagnostics and emission compliance logs in armored ground vehicles exposed to shock, vibration, and wide ambient swings. IC Role / Device Role / Timing Role: Ruggedized event logger with page-write efficiency for burst data capture; integrated hardware write protection prevents corruption during ignition transients. Use Value: Achieves 10,000-cycle endurance under frequent logging intervals while surviving MIL-STD-810G mechanical shock profiles. | Use Scenario: Capturing housekeeping telemetry (voltage, temperature, radiation dose) during orbital eclipse periods where power is constrained. IC Role / Device Role / Timing Role: Low-quiescent-current nonvolatile buffer (300 µA CMOS standby) that retains data through multi-hour power-downs. Use Value: Maintains 10-year data retention without refresh, satisfying ECSS-Q-ST-60-13C long-term mission data integrity requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC256-90UM/883 | 10 ms page write cycle; standard endurance (10K cycles); same pinout and voltage | Higher write latency; suited for infrequent configuration updates | Select when cost sensitivity outweighs write-speed requirements and full 3 ms performance is unnecessary |
| AT28HC256E-90UM/883 | 100,000-cycle endurance rating; identical 90 ns access and 3 ms write timing | Extended lifecycle for high-write-frequency telemetry or logging systems | Choose when field-replaceable units require >10K reprogramming cycles over operational lifetime |
Compared with AT28HC256F-90UM/883, the AT28HC256-90UM/883 trades faster write speed for lower cost, while the AT28HC256E-90UM/883 delivers 10× endurance without sacrificing timing - enabling selection based on program frequency and lifecycle assurance needs.
Availability
AT28HC256F-90UM/883 is available at Aetrix Electronics and suitable for avionics flight control, military radar calibration, tactical vehicle engine management, and spacecraft telemetry logging requiring stable component supply under extended temperature and radiation-hardened conditions.
Supply support for AT28HC256F-90UM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor manufacturer specializing in microcontrollers, analog devices, and nonvolatile memory solutions for industrial, automotive, aerospace, and defense markets.
The AT28HC256 product line delivers high-reliability parallel EEPROMs engineered for mission-critical systems requiring guaranteed data integrity, extended temperature operation, and MIL-STD-883 qualification.
FAQ
What is the maximum page write cycle time for AT28HC256F-90UM/883?
The AT28HC256F-90UM/883 has a maximum page write cycle time of 3 ms, as confirmed in Table 6-4 (Page Mode Characteristics) of the DS20006352A datasheet. This distinguishes it from the standard AT28HC256-90UM/883 variant, which specifies 10 ms. The 3 ms timing applies to all 1–64 byte page writes within the same address page (A6–A14 constant).
Does AT28HC256F-90UM/883 support both hardware and software write protection?
Yes, AT28HC256F-90UM/883 implements dual-layer write protection: hardware features include VCC sensing (~3.8V threshold), 5 ms power-on delay, noise filtering (<15 ns pulse rejection), and standard CE/OE/WE logic gating; software protection uses a 3-byte command sequence (AAh/55h/A0h) to enable/disable SDP mode, as detailed in Sections 6.11–6.12 of the datasheet.
What package type is used for AT28HC256F-90UM/883?
AT28HC256F-90UM/883 is packaged in a 30-pin ceramic Pin Grid Array (PGA), designated "UM" in the part marking per Section 7.1 (Package Marking Information). This package complies with MIL-STD-1835 U-configuration, features hermetic sealing, and is qualified per MIL-STD-883 for high-reliability applications.
How is write completion detected on AT28HC256F-90UM/883?
AT28HC256F-90UM/883 supports two independent write-completion detection methods: DATA Polling (reading I/O7 returns complemented data until write completes, then true data) and Toggle Bit (I/O6 toggles between 0 and 1 during write, then stabilizes). Both are characterized in Sections 6.14–6.17 and require no external components.
Is AT28HC256F-90UM/883 compatible with standard JEDEC byte-wide memory interfaces?
Yes, AT28HC256F-90UM/883 implements a JEDEC-approved byte-wide pinout (Section 1, Features), matching industry-standard parallel EEPROM layouts. Its address (A0–A14), data (I/O0–I/O7), and control (CE, OE, WE) signals align with common microprocessor bus protocols, enabling drop-in replacement in legacy 8-bit systems without PCB redesign.
AT28HC256F-90UM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-BCPGA
- Packaging:
- Box
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-CPGA (13.97x16.51)
AT28HC256F-90UM/883 FAQ
1.How can I place an order for AT28HC256F-90UM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC256F-90UM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC256F-90UM/883 reliable?
The price and inventory of AT28HC256F-90UM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC256F-90UM/883 is usually 5 days.
3.What payment methods are accepted for AT28HC256F-90UM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC256F-90UM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC256F-90UM/883?
AT28HC256F-90UM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC256F-90UM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC256F-90UM/883?
For technical support, including AT28HC256F-90UM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC256F-90UM/883 requirements.
6.How does Aetrix verify that AT28HC256F-90UM/883 is sourced from the original manufacturer or authorized distributors?
All AT28HC256F-90UM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC256F-90UM/883 meets industry standards.
7.What is the process for return or replacement of AT28HC256F-90UM/883?
All AT28HC256F-90UM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC256F-90UM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC256F-90UM/883 part is unused and in its original packaging.
Return procedure for AT28HC256F-90UM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC256F-90UM/883 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

