My Inquiry
My Account
Microchip Technology AT28HC64B-12SC
- Part No.:
- AT28HC64B-12SC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28HC64B-12SC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,271
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC64B-12SC from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 55 ns read access time, 10 ms page write cycle, and CMOS/TTL-compatible I/O. It operates from a single 5 V ±10% supply and supports hardware/software data protection for industrial control and embedded firmware storage applications.
For engineers reviewing the AT28HC64B-12SC datasheet, AT28HC64B-12SC pinout, AT28HC64B-12SC application, or AT28HC64B-12SC equivalent, this page delivers verified timing parameters, JEDEC-compliant pin functions, page-write endurance (100,000 cycles), software data protection enable/disable sequences, and validated green-packaging options - all specific to the -12SC variant in 28-lead SOIC.
Technical Context
The AT28HC64B-12SC implements a parallel interface with CE/OE/WE control logic enabling SRAM-like read/write operation without external timing components. Its internal 64-byte page register latches address and data during page writes, freeing the bus after initiation.
Write completion is signaled via DATA polling on I/O7 or toggle-bit behavior on I/O6, both usable at any point during tWC. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable nonvolatile storage |
| Read Access Time | 120 ns max - defines minimum clock-to-data latency in microcontroller memory-mapped interfaces |
| Page Write Cycle | 10 ms max - determines maximum time host must wait before initiating next access after multi-byte write |
| Active Current | 40 mA max - sets power budget for active read/write bursts in battery-sensitive systems |
| Standby Current | 100 µA CMOS - enables low-power retention in always-on embedded controllers |
| Endurance | 100,000 write/erase cycles - supports field-updatable calibration tables or configuration logs |
| Data Retention | 10 years at 85°C - ensures long-term reliability in industrial temperature environments |
Pinout & Package
AT28HC64B-12SC is supplied in a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC) package per JEDEC MS-013, compliant with RoHS and green (Pb/halide-free) requirements.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 bytes; A6–A12 define page boundaries for 64-byte writes |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for valid read access |
| OE | Output Enable | Active-low output gate; controls data bus tristate during reads and enables DATA polling |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; initiates byte or page write |
| I/O0–I/O7 | Bi-directional Data Bus | 8-bit parallel data path; I/O7 used for DATA polling, I/O6 for toggle-bit write status detection |
| VCC | Power Supply | +5 V ±10% supply; device inhibits writes if voltage drops below 3.8 V |
| GND | Ground Reference | Signal and power return; required for stable read/write margins and noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-wide Pinout | Direct drop-in replacement for industry-standard 28-pin parallel EEPROMs without PCB redesign |
| 64-byte Page Write | Reduces firmware update time by up to 64× vs. byte-write; requires no external address sequencing logic |
| Software Data Protection (SDP) | User-enabled 3-byte command sequence prevents accidental writes during power transitions or debug sessions |
| Hardware Write Inhibit | VCC sense, 5 ms power-on delay, and 15 ns noise filtering eliminate spurious writes in noisy industrial environments |
| Device Identification Area | 64 extra bytes (1FC0H–1FFFH) accessible at 12 V on A9 for unique serialization or calibration data storage |
Applications
| Industrial PLC Configuration Storage | Automotive ECU Calibration Memory |
|---|---|
|
Use Scenario: Storing runtime-configurable I/O mapping and alarm thresholds in programmable logic controllers operating continuously at 85°C. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed via 8051 or ARM Cortex-M3 memory-mapped bus with 120 ns read timing compliance. Use Value: 10-year data retention and 100,000-cycle endurance ensure field reliability across 15+ year product lifecycles without recalibration. |
Use Scenario: Holding engine calibration tables updated during dealership service flashes, requiring secure write protection against unintended overwrites. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced to CAN controller's host MCU; SDP enabled to block writes unless authenticated 3-byte unlock sequence issued. Use Value: Hardware VCC-sense + software lock prevents corruption during vehicle battery transients or brownout conditions. |
| Medical Device Parameter Backup | Networking Equipment Bootloader Storage |
|
Use Scenario: Preserving user-adjusted therapy parameters in portable infusion pumps where power loss must not erase critical settings. IC Role / Device Role / Timing Role: Standby current of 100 µA enables >1 year backup from coin-cell when main power fails; page write completes within 10 ms during safe shutdown. Use Value: Guaranteed data integrity via DATA polling allows deterministic recovery without timeout-based retries. |
Use Scenario: Storing boot code checksums and FPGA configuration bitstreams in enterprise switches requiring field-upgradable firmware. IC Role / Device Role / Timing Role: Memory-mapped as lower 64 KB of address space; 120 ns access meets timing budgets for 8 MHz Z80 or MIPS32 boot sequences. Use Value: JEDEC pinout ensures compatibility with legacy board designs while green packaging satisfies EU RoHS compliance mandates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECB90N6 | 64 Mbit capacity, 90 ns access, 3.3 V core with 5 V tolerant I/O | Higher density and lower voltage operation; lacks software data protection and 12 V identification area | Choose for 3.3 V systems needing larger memory; verify SDP absence does not impact security requirements |
| ON Semiconductor CAT28C64B-120WI | Same 64 Kbit size and 120 ns speed, but only offers hardware protection (no SDP) | Industrial temp range (-40°C to 85°C) matches AT28HC64B-12SC, but no 12 V device ID feature | Choose when software lock is unnecessary and cost sensitivity outweighs feature parity |
Compared with ST M28W640ECB90N6 and CAT28C64B-120WI, the AT28HC64B-12SC uniquely combines JEDEC pinout compatibility, integrated software data protection, and dedicated 12 V-programmable device identification memory - making it optimal for legacy-replacement and safety-critical firmware storage where write security and traceability are mandatory.
Availability
AT28HC64B-12SC is available at Aetrix Electronics and suitable for industrial PLCs, automotive ECUs, medical device parameter backup, and networking equipment bootloader storage requiring stable component supply, long-lifecycle support, and green packaging compliance.
Supply support for AT28HC64B-12SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel parallel EEPROMs including the AT28HC64B family.
The AT28HC64B product line was designed for reliable, pin-compatible replacement of aging EPROM and early EEPROM solutions in industrial and automotive control systems requiring robust write protection and long-term data retention.
FAQ
What is the maximum page write cycle time for AT28HC64B-12SC?
The AT28HC64B-12SC has a maximum page write cycle time of 10 ms under standard operation. This value is guaranteed across the commercial temperature range (0°C to 70°C) and defines the longest duration the host system must wait before issuing a new read or write command after initiating a page write. The 2 ms option is not available for the -12SC variant.
Does AT28HC64B-12SC support software data protection (SDP)?
Yes, AT28HC64B-12SC fully supports software data protection. SDP is disabled by default and can be enabled or disabled using documented 3-byte command sequences written to specific addresses (1555H, 0AAAH, etc.). Once enabled, all writes require reissuing the unlock sequence - a critical safeguard against accidental overwrites during power transitions or debugging.
What package type is used for AT28HC64B-12SC?
AT28HC64B-12SC is packaged in a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC) per JEDEC MS-013. This green (Pb/halide-free) package measures 17.7–18.1 mm × 7.4–7.6 mm × 2.35–2.65 mm and features gull-wing leads for surface-mount assembly compatibility with standard reflow profiles.
How is write completion detected on AT28HC64B-12SC?
AT28HC64B-12SC provides two hardware-supported methods: DATA polling on I/O7 (complement of last written byte until completion) and toggle-bit detection on I/O6 (repeated toggling until write ends). Both methods are usable at any time during the write cycle and require no additional timing components - enabling deterministic host firmware control.
Is AT28HC64B-12SC compatible with 3.3 V systems?
No, AT28HC64B-12SC requires a single 5 V ±10% supply (4.5 V to 5.5 V) and is not 3.3 V compatible. Its inputs are CMOS/TTL-compatible but do not tolerate 3.3 V logic levels as supply voltage; interfacing with 3.3 V microcontrollers requires level-shifting circuitry on address, data, and control lines to prevent damage or unreliable operation.
AT28HC64B-12SC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28HC64B-12SC FAQ
1.How can I place an order for AT28HC64B-12SC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-12SC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-12SC reliable?
The price and inventory of AT28HC64B-12SC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-12SC is usually 5 days.
3.What payment methods are accepted for AT28HC64B-12SC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-12SC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64B-12SC?
AT28HC64B-12SC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-12SC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-12SC?
For technical support, including AT28HC64B-12SC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-12SC requirements.
6.How does Aetrix verify that AT28HC64B-12SC is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-12SC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-12SC meets industry standards.
7.What is the process for return or replacement of AT28HC64B-12SC?
All AT28HC64B-12SC units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-12SC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-12SC part is unused and in its original packaging.
Return procedure for AT28HC64B-12SC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC64B-12SC Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
