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Microchip Technology AT28HC64B-12SI

Part No.:
AT28HC64B-12SI
Manufacturer:
Microchip Technology
Category:
Memory
Package:
28-SOIC (0.295", 7.50mm Width)
Datasheet:
AetrixAT28HC64B-12SI.pdf
Description:
IC EEPROM 64KBIT PARALLEL 28SOIC
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:4,946

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Product details

Overview

AT28HC64B-12SI from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 120 ns maximum read access time, CMOS/TTL-compatible I/O, and industrial temperature range (–40°C to +85°C). It supports automatic 1–64-byte page writes, hardware/software data protection, and DATA polling/toggle-bit write completion detection - used in embedded system configuration storage, firmware parameter retention, and boot loader nonvolatile data tables.

For engineers reviewing the AT28HC64B-12SI datasheet, AT28HC64B-12SI pinout, AT28HC64B-12SI application, or AT28HC64B-12SI equivalent, key selection criteria include page-write timing (10 ms standard), VCC=5 V ±10% operation, 100 µA CMOS standby current, endurance (100,000 cycles), and JEDEC-compliant 28-pin SOIC packaging for legacy board compatibility.

Technical Context

The AT28HC64B-12SI operates as a drop-in parallel memory replacement for SRAM-based read/write interfaces without external timing logic. Its internal 64-byte page register latches address and data during write initiation, freeing the bus for concurrent operations while an internal timer executes the programming cycle.

Write completion is verified via dual methods: DATA polling on I/O7 (complement → true data transition) and toggle-bit behavior on I/O6 (toggling ceases at completion). Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs; software protection uses a 3-byte command sequence to enable/disable write lock.

Key Specifications

Parameter Value and Actual Design Meaning
Memory Size64 Kbit (8,192 × 8 bits) - supports full byte-addressable access without banking or interleaving.
Read Access Time120 ns max - meets timing requirements for 8 MHz CPU bus interfaces with no wait states.
Page Write Cycle10 ms max (standard) - enables burst programming of up to 64 bytes with single command initiation.
Endurance100,000 write/erase cycles - suitable for field-updatable calibration data or infrequent configuration changes.
Standby Current100 µA (CMOS) - enables low-power retention in battery-backed systems or sleep-mode operation.
VCC Supply5 V ±10% - compatible with legacy 5 V logic families and eliminates need for dedicated voltage regulators.
Data Retention10 years - ensures long-term reliability of stored parameters without refresh or backup power.

Pinout & Package

AT28HC64B-12SI is packaged in a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC) per JEDEC MS-013, with lead pitch 1.27 mm and body dimensions 17.7–18.1 mm × 7.4–7.6 mm × 2.35–2.65 mm.

Pin/Terminal Circuit Role Design Meaning
A0–A12Address Inputs13-bit address bus for full 8K-word decoding; A6–A12 define page boundaries for 64-byte page writes.
I/O0–I/O7Bidirectional Data BusTrue 8-bit parallel interface; supports read output drive and write input latching without direction control.
CEChip EnableActive-low chip select; must be low for read/write access; high-Z output when asserted high.
OEOutput EnableActive-low output gate; controls data bus drivers independently of CE to prevent bus contention.
WEWrite EnableActive-low write strobe; falling edge latches address/data; rising edge initiates internal programming.
GND / VCCPower TerminalsGround reference and 5 V supply; decoupling required within 10 mm of pins per JEDEC layout guidelines.
NCNo ConnectUnbonded pin; must remain floating - no external connection or pull-up/down allowed.

Key Features

Feature Design Value
JEDEC Byte-wide PinoutDirect replacement for industry-standard 28-pin parallel EPROMs and SRAMs - no PCB redesign needed.
Automatic Page WriteInternal 64-byte latch allows sequential loading of 1–64 bytes within 150 µs intervals, reducing host CPU overhead.
DATA Polling & Toggle BitDual asynchronous write-complete detection methods eliminate need for fixed delay timers or status registers.
Hardware + Software ProtectionVCC sensing, 5 ms power-on delay, and 3-byte SDP command prevent accidental writes during power transitions or debug sessions.
Industrial Temperature Range–40°C to +85°C operation validated across full voltage and timing specs - suitable for automotive under-hood and industrial PLC environments.

Applications

Industrial PLC Configuration Storage Medical Device Calibration Data Retention

Use Scenario: Storing user-configurable I/O mapping, alarm thresholds, and scaling factors in programmable logic controllers deployed in factory automation.

IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via parallel bus during boot and runtime reconfiguration; 120 ns read timing aligns with 8 MHz microcontroller bus cycles.

Use Value: Eliminates need for battery-backed SRAM; 100,000-cycle endurance supports decades of field updates; 10-year data retention ensures parameter integrity across equipment lifecycle.

Use Scenario: Holding factory-calibrated sensor offsets, gain coefficients, and safety-critical operational limits in portable diagnostic instruments.

IC Role / Device Role / Timing Role: Secure parameter store with software data protection enabled - prevents unauthorized modification during service or firmware update.

Use Value: Hardware VCC-sense and SDP ensure calibration data remains intact during brown-out events or accidental debug probe attachment.

Legacy Embedded System Boot Loader Parameters Telecom Line Card Firmware Patch Storage

Use Scenario: Storing bootloader version, flash partition addresses, and secure boot keys in MIPS- or ARM7-based networking appliances with aging PCB layouts.

IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to CPU address/data bus; JEDEC pinout matches obsolete 27C64 footprint.

Use Value: Enables drop-in replacement of discontinued EPROMs without trace routing changes; 5 V tolerance simplifies integration with legacy 5 V logic rails.

Use Scenario: Holding hot-swappable firmware patches and feature-enable flags in carrier-grade DSLAM line cards requiring zero-downtime updates.

IC Role / Device Role / Timing Role: Dual-page write capability allows atomic patch loading: one page holds active code, second holds updated version before atomic swap.

Use Value: 10 ms page write enables sub-100 ms patch commits; DATA polling allows precise synchronization with FPGA-based memory controllers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Alternative Part Technical Difference Application Difference Selection Advice
ST M28W640ECB90N664 Mbit (8M × 8), 90 ns access, 3.3 V core with 5 V tolerant I/O - larger density, lower voltage, different pinout.Requires PCB redesign due to 48-pin TSOP-II package and 3.3 V supply dependency.Select only when migrating to higher-density, lower-power designs with new layout resources.
Microchip 25LC640A-I/SN64 Kbit SPI EEPROM, 10 MHz interface, 5 V operation - serial interface, no parallel bus support.Eliminates 28-pin footprint; requires firmware driver change from memory-mapped to SPI protocol stack.Choose for space-constrained boards where serial interface suffices and parallel bus lines are unavailable.

Compared with ST M28W640ECB90N6 and Microchip 25LC640A-I/SN, the AT28HC64B-12SI uniquely preserves legacy 28-pin SOIC parallel bus compatibility, 5 V-only operation, and JEDEC pinout - making it the only direct replacement for existing AT28HC64B-12xx designs without hardware or software revision.

Availability

AT28HC64B-12SI is available at Aetrix Electronics and suitable for industrial PLC configuration storage, medical device calibration data retention, and legacy embedded system boot loader parameter management requiring stable component supply and long-term obsolescence mitigation.

Supply support for AT28HC64B-12SI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs, with design centers across the US, Europe, and Asia.

The AT28HC64B product line was engineered for robust, pin-compatible replacement of EPROM and battery-backed SRAM in industrial and telecom systems requiring reliable, low-power, parallel-interface nonvolatile storage.

FAQ

What is the maximum page write cycle time for AT28HC64B-12SI?

The AT28HC64B-12SI has a maximum page write cycle time of 10 ms under standard operation. This value is guaranteed across the full industrial temperature range (–40°C to +85°C) and 5 V ±10% supply. The AT28HC64BF variant offers a faster 2 ms option, but AT28HC64B-12SI strictly adheres to the 10 ms specification as confirmed in its AC characteristics table.

Does AT28HC64B-12SI support both hardware and software data protection?

Yes, AT28HC64B-12SI implements dual-layer protection: hardware features include VCC sensing (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs; software protection uses a three-byte command sequence (AAh→55h→A0h) to enable/disable write lock. Both mechanisms operate independently and are fully functional in the AT28HC64B-12SI.

What package type is used for AT28HC64B-12SI?

AT28HC64B-12SI uses a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC) package, designated as "28S" in Atmel's ordering matrix. Its dimensions conform to JEDEC MS-013, with 1.27 mm lead pitch and body size 17.7–18.1 mm × 7.4–7.6 mm - identical to legacy 27C64 and 6264 SRAM footprints.

Can AT28HC64B-12SI be used in place of faster-speed variants like AT28HC64B-70SI?

Yes, AT28HC64B-12SI is functionally compatible with AT28HC64B-70SI and AT28HC64B-90SI - all share identical pinout, command set, protection features, and DC specifications. The "12" suffix denotes 120 ns read access time, so timing-critical systems designed for 70 ns may require validation, but logic-level and protocol behavior are fully interchangeable.

How is write completion detected on AT28HC64B-12SI?

AT28HC64B-12SI provides two independent, asynchronous methods: DATA polling monitors I/O7 (complement → true data transition), and toggle-bit detection observes I/O6 (toggling stops at completion). Both methods work during any phase of the write cycle and require no additional hardware - enabling deterministic timing control in bare-metal or RTOS environments.

AT28HC64B-12SI Specifications

Product attributes
Attribute value
Manufacturer:
Microchip Technology
Series:
-
Package/Case:
28-SOIC (0.295", 7.50mm Width)
Packaging:
Tube
Product Status:
Obsolete
Programmable:
Not Verified
Memory Type:
Non-Volatile
Memory Format:
EEPROM
Technology:
EEPROM
Memory Size:
64Kbit
Memory Organization:
8K x 8
Memory Interface:
Parallel
Clock Frequency:
-
Write Cycle Time - Word, Page:
10ms
Access Time:
120 ns
Voltage - Supply:
4.5V ~ 5.5V
Operating Temperature:
-40°C ~ 85°C (TC)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
28-SOIC

AT28HC64B-12SI FAQ

1.How can I place an order for AT28HC64B-12SI through Aetrix?

Please submit a Request for Quotation (RFQ) for AT28HC64B-12SI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT28HC64B-12SI reliable?

The price and inventory of AT28HC64B-12SI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-12SI is usually 5 days.

3.What payment methods are accepted for AT28HC64B-12SI?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-12SI transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT28HC64B-12SI?

AT28HC64B-12SI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT28HC64B-12SI order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT28HC64B-12SI?

For technical support, including AT28HC64B-12SI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-12SI requirements.

6.How does Aetrix verify that AT28HC64B-12SI is sourced from the original manufacturer or authorized distributors?

All AT28HC64B-12SI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-12SI meets industry standards.

7.What is the process for return or replacement of AT28HC64B-12SI?

All AT28HC64B-12SI units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-12SI, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT28HC64B-12SI part is unused and in its original packaging.

Return procedure for AT28HC64B-12SI:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

AT28HC64B-12SI Tags

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