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Microchip Technology AT28HC64B-12SU-T
- Part No.:
- AT28HC64B-12SU-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28HC64B-12SU-T.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:482
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Product details
Overview
AT28HC64B-12SU-T from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 120 ns read access time, hardware/software data protection, and page write capability supporting up to 64-byte writes in ≤10 ms. It operates from a single 5 V ±10% supply and targets firmware storage, configuration memory, and calibration data retention in industrial control modules.
For engineers reviewing the AT28HC64B-12SU-T datasheet, AT28HC64B-12SU-T pinout, AT28HC64B-12SU-T application, or AT28HC64B-12SU-T equivalent, key selection criteria include verified 120 ns tACC timing, CMOS/TTL-compatible I/O, 100 µA standby current, and software data protection enable/disable command sequences confirmed for this SOIC-28 variant.
Technical Context
The AT28HC64B-12SU-T implements a parallel interface with independent CE/OE/WE control logic enabling SRAM-like read/write cycles without external timing components. Its internal 64-byte page register latches address and data during page write operations, freeing the bus after initiation.
Write completion detection is supported via dual methods: DATA polling on I/O7 (complement-to-data during write, true data upon completion) and toggle-bit behavior on I/O6, both usable at any point during the write cycle. Hardware write inhibition activates below 3.8 V VCC and incorporates noise filtering for WE/CE pulses <15 ns.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), sufficient for bootloader code or multi-parameter calibration tables |
| Read Access Time (tACC) | 120 ns maximum - defines minimum CPU wait-state requirement for zero-wait-state interfacing |
| Page Write Cycle Time | 10 ms maximum - enables burst programming of configuration blocks without host intervention |
| VCC Supply | 5 V ±10% - compatible with legacy 5 V logic systems without level-shifting |
| Standby Current (ISB1) | 100 µA maximum - supports low-power sleep modes in battery-backed systems |
| Endurance | 100,000 write/erase cycles - ensures field-upgradeable firmware retains integrity over product lifetime |
| Data Retention | 10 years at 85°C - validated for industrial temperature operation without refresh |
Pinout & Package
AT28HC64B-12SU-T is supplied in a 28-lead SOIC (Small Outline Integrated Circuit) package, 0.300" wide, RoHS-compliant and green (Pb/halide-free). Pin layout follows JEDEC-standard byte-wide configuration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path; I/O7 used for DATA polling, I/O6 for toggle-bit write status indication |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read access |
| OE | Output Enable | Active-low output control; disables outputs to high-Z when high, preventing bus contention |
| WE | Write Enable | Active-low write strobe; initiates byte or page write on falling edge with CE low |
| GND / VCC | Power Terminals | Ground reference and 5 V supply; decoupling capacitor required within 1 cm of pins per datasheet layout guidance |
| NC | No Connect | Pins 1 and 28 are unconnected; must remain floating - no PCB trace or pull-up/down |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Operation | Up to 64 bytes written in single internal cycle (≤10 ms), reducing host CPU overhead vs. 8K individual byte writes |
| Software Data Protection (SDP) | User-enabled/disabled via documented 3-byte command sequence (AAh/55h/A0h); prevents accidental writes during power transitions |
| Hardware Write Inhibition | Automatic disable below 3.8 V VCC + 5 ms power-on delay + noise filtering (<15 ns pulses rejected) - eliminates brown-out corruption |
| DATA Polling & Toggle Bit | Dual asynchronous write-complete detection: I/O7 complement/data toggle and I/O6 state toggling - no timer dependency in host firmware |
| Device Identification Area | 64 extra bytes (1FC0h–1FFFh) accessible via 12 V on A9 - enables unique serialization or revision tracking without external memory |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Memory |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and alarm thresholds in programmable logic controllers operating continuously at 85°C ambient. IC Role / Device Role / Timing Role: Nonvolatile configuration EEPROM interfaced directly to microcontroller's parallel bus; 120 ns tACC allows tight timing integration with 8-bit MCUs. Use Value: 10-year data retention at 85°C and 100,000 endurance cycles ensure parameter integrity across 15+ year equipment lifetimes without maintenance. | Use Scenario: Holding factory-calibrated sensor offsets and gain coefficients in portable diagnostic instruments requiring FDA-compliant traceability. IC Role / Device Role / Timing Role: Secure calibration data vault using SDP commands; device ID area (1FC0h–1FFFh) stores serial number and calibration date under 12 V A9 access. Use Value: Hardware + software write protection prevents field corruption during battery swaps or ESD events, meeting IEC 60601-1 safety requirements. |
| Automotive Body Control Module (BCM) | Telecom Line Card Firmware Storage |
Use Scenario: Storing seat/mirror position presets and lighting profiles in BCMs exposed to -40°C to 85°C thermal cycling. IC Role / Device Role / Timing Role: Parallel EEPROM replacing older EPROMs; SOIC-28 footprint enables drop-in replacement in legacy designs with no PCB rework. Use Value: Single 5 V supply eliminates need for auxiliary regulators; 100 µA standby current minimizes parasitic drain on vehicle battery during ignition-off periods. | Use Scenario: Storing boot firmware images and port initialization scripts in carrier-grade DSLAM line cards requiring hot-swap capability. IC Role / Device Role / Timing Role: Firmware storage element accessed by DSP during power-up; page write allows rapid field updates of feature patches without full erase cycles. Use Value: 64-byte page write reduces update time by >98% vs. byte-by-byte programming - critical for minimizing service downtime during firmware rollouts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC64B-12JU | Same die, PLCC-32 package instead of SOIC-28; identical 120 ns timing and 10 ms page write | Requires different PCB footprint and reflow profile; suited for socketed or high-vibration environments | Select when mechanical robustness or socket-based field upgrades are prioritized over board space |
| ST M48T02-120MH6 | 64 Kbit parallel EEPROM with built-in lithium backup and real-time clock; 120 ns access but no page write or SDP | Provides time-stamped logging capability; lacks software protection and fast multi-byte writes | Choose only if integrated RTC and battery-backed timekeeping outweigh loss of page write efficiency and SDP security |
Compared with AT28HC64B-12JU, the AT28HC64B-12SU-T saves board area and simplifies assembly; versus ST M48T02-120MH6, it delivers faster firmware updates and stronger write-integrity safeguards but requires external timekeeping.
Availability
AT28HC64B-12SU-T is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, automotive body electronics, and telecom infrastructure requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AT28HC64B-12SU-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT28HC64B product line delivers high-reliability parallel EEPROMs optimized for industrial and automotive applications demanding long data retention, robust write protection, and JEDEC-standard interoperability.
FAQ
What is the maximum page write cycle time for AT28HC64B-12SU-T?
The maximum page write cycle time for AT28HC64B-12SU-T is 10 ms, as specified in the official Atmel datasheet (document 0274L–PEEPR). This value applies to the standard version; the optional AT28HC64BF variant achieves 2 ms but is not applicable to the AT28HC64B-12SU-T. The 10 ms timing is guaranteed across the full industrial temperature range (-40°C to +85°C).
Does AT28HC64B-12SU-T support both hardware and software write protection?
Yes, AT28HC64B-12SU-T implements dual-layer write protection. Hardware protection includes VCC sense (inhibits writes below 3.8 V), 5 ms power-on delay, and noise filtering on WE/CE inputs. Software Data Protection (SDP) is enabled or disabled via a documented three-byte command sequence (AAh/55h/A0h for enable; AAh/55h/80h/AAh/20h for disable), which persists through power cycles.
What package type is used for AT28HC64B-12SU-T?
AT28HC64B-12SU-T uses a 28-lead SOIC (Small Outline Integrated Circuit) package, 0.300" wide, with green (Pb/halide-free) construction. The "SU" suffix explicitly denotes this SOIC-28 variant, distinguishing it from the PLCC-32 ("JU") and TSOP-28 ("TU") versions. Pin 1 identifier and dimensions conform to JEDEC MS-013.
How is write completion detected on AT28HC64B-12SU-T?
AT28HC64B-12SU-T supports two independent, asynchronous write completion detection methods: DATA polling on I/O7 (returns complement of last written data until complete, then true data) and toggle-bit behavior on I/O6 (toggles between 0 and 1 during write, stabilizes upon completion). Both methods require no external timing components and can be polled at any time during the write cycle.
Is AT28HC64B-12SU-T compatible with standard 5 V TTL and CMOS logic levels?
Yes, AT28HC64B-12SU-T features CMOS and TTL compatible inputs and outputs. Input thresholds meet VIH ≥ 2.0 V and VIL ≤ 0.8 V; output drive meets VOH ≥ 2.4 V (at -400 µA) and VOL ≤ 0.4 V (at 2.1 mA), ensuring reliable interfacing with legacy 5 V microcontrollers, FPGAs, and ASICs without level shifters.
AT28HC64B-12SU-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28HC64B-12SU-T FAQ
1.How can I place an order for AT28HC64B-12SU-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-12SU-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-12SU-T reliable?
The price and inventory of AT28HC64B-12SU-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-12SU-T is usually 5 days.
3.What payment methods are accepted for AT28HC64B-12SU-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-12SU-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64B-12SU-T?
AT28HC64B-12SU-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-12SU-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-12SU-T?
For technical support, including AT28HC64B-12SU-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-12SU-T requirements.
6.How does Aetrix verify that AT28HC64B-12SU-T is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-12SU-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-12SU-T meets industry standards.
7.What is the process for return or replacement of AT28HC64B-12SU-T?
All AT28HC64B-12SU-T units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-12SU-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-12SU-T part is unused and in its original packaging.
Return procedure for AT28HC64B-12SU-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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