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Microchip Technology AT28HC64B-70JC
- Part No.:
- AT28HC64B-70JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28HC64B-70JC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:2,537
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Product details
Overview
AT28HC64B-70JC from Microchip Technology (formerly Atmel) is a 64 Kbit parallel EEPROM organized as 8,192 × 8 bits, featuring 55 ns read access time, JEDEC-standard byte-wide pinout, and hardware/software data protection. It supports page write (1–64 bytes), DATA polling and toggle-bit write completion detection, and operates across commercial temperature range (0°C to 70°C) with single 5 V ±10% supply - used in embedded system configuration storage and firmware parameter retention.
For engineers reviewing the AT28HC64B-70JC datasheet, AT28HC64B-70JC pinout, AT28HC64B-70JC application, or AT28HC64B-70JC equivalent, key selection considerations include its 70 ns access timing grade, PLCC-32 package, page-write cycle time (10 ms standard / 2 ms optional), CMOS/TTL compatibility, and dual-layer data protection for industrial control and telecom equipment boot memory.
Technical Context
The AT28HC64B-70JC implements a static RAM-compatible interface with CE/OE/WE three-line control logic, enabling seamless integration into legacy microcontroller buses without external timing circuitry. Its internal 64-byte page register latches address and data during page writes, freeing the bus for concurrent operations.
Write completion is verified via two independent methods: DATA polling on I/O7 (complement-to-data during write, true data after completion) and toggle-bit behavior on I/O6 (toggling until write ends). Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8) - sufficient for bootloader parameters, calibration tables, or device ID storage in resource-constrained systems |
| Read Access Time | 70 ns - meets timing requirements for 14 MHz bus interfaces with adequate setup/hold margins |
| Page Write Cycle | 10 ms max (standard) - enables efficient bulk updates without CPU blocking; optional 2 ms version available |
| Supply Voltage | 5 V ±10% - compatible with legacy 5 V logic families and mixed-voltage board designs |
| Standby Current | 100 µA (CMOS) - supports low-power sleep modes in battery-backed or energy-sensitive applications |
| Endurance | 100,000 write/erase cycles - suitable for field-updatable configuration storage with multi-year service life |
| Data Retention | 10 years - ensures long-term reliability of stored settings without refresh overhead |
Pinout & Package
AT28HC64B-70JC is supplied in a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package per JEDEC MS-016, Variation AE. Pin 1 identifier is marked by a corner chamfer; pins 1 and 17 are no-connect (NC).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; A6–A12 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional Data Bus | CMOS/TTL-compatible 8-bit data path; carries latched write data and asserted read outputs |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; initiates write when pulsed low with OE high |
| OE | Output Enable | Active-low output gate; controls data bus drive during reads and enables DATA polling/toggle-bit monitoring |
| WE | Write Enable | Active-low write strobe; falling edge latches address; rising edge latches data; used with CE for robust write initiation |
| VCC, GND | Power Supply | Single 5 V ±10% supply with decoupling required; ground reference for all I/O and internal logic |
| NC | No Connect | Pins 1 and 17 are unconnected - must remain floating per datasheet; no PCB routing or termination needed |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC-standard byte-wide pinout | Ensures drop-in compatibility with existing 28-pin and 32-pin EEPROM footprints and socketed designs |
| 64-byte page write with auto-latching | Reduces host CPU intervention time by up to 64× vs. byte-by-byte writes; eliminates external address/data hold logic |
| Hardware + software data protection | VCC sensing, 5 ms power-on delay, and 3-byte SDP command sequence prevent accidental writes during power transitions or firmware bugs |
| DATA polling and toggle-bit detection | Enables real-time write status monitoring without fixed delays - critical for deterministic real-time system response |
| Extra 64-byte identification area | Accessible at 1FC0H–1FFFH with 12 V on A9; supports unique device serialization, revision tracking, or secure key storage |
Applications
| Industrial PLC Configuration Storage | Telecom Line Card Parameter Retention |
|---|---|
Use Scenario: Storing I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers that undergo infrequent but critical field updates. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced directly to an 8-bit microcontroller bus; accessed during boot and on-demand reconfiguration. Use Value: 100,000-cycle endurance and 10-year data retention ensure reliable operation over extended maintenance intervals without backup batteries. | Use Scenario: Holding DSP coefficient sets, port enable/disable states, and calibration offsets in carrier-grade line cards requiring hot-swap capability and zero-downtime updates. IC Role / Device Role / Timing Role: Parallel EEPROM acting as boot-time parameter source for FPGA or DSP; accessed via shared address/data bus with tight 70 ns timing compliance. Use Value: Page write reduces update latency to ≤10 ms per 64-byte block, enabling rapid field upgrades without interrupting live traffic paths. |
| Medical Device Calibration Memory | Automotive Body Control Module Settings |
Use Scenario: Storing sensor offset corrections, gain coefficients, and safety-critical operational limits in portable diagnostic equipment subject to periodic recalibration. IC Role / Device Role / Timing Role: Secure nonvolatile memory with software data protection enabled; accessed only during calibration mode via dedicated MCU interface. Use Value: Dual-layer protection (VCC sense + SDP) prevents corruption during brown-out events or unintended firmware execution, meeting IEC 62304 traceability requirements. | Use Scenario: Retaining user preferences (window position, mirror angle, lighting profiles) and adaptive learning values in body control units exposed to wide thermal cycling (-40°C to +85°C). IC Role / Device Role / Timing Role: Industrial-temperature-rated EEPROM (via AT28HC64B-70JI variant) operating as persistent settings store; interfaced to 8-bit CAN node MCU. Use Value: 100 µA standby current minimizes parasitic drain on vehicle battery during extended parking periods. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-70JC | Same pinout and function but lacks software data protection and extra 64-byte ID area; lower cost | Suitable for cost-sensitive, non-security-critical applications where write protection is handled externally | Select when SDP and device ID features are unnecessary and BOM cost optimization is primary |
| MX28LV640BTC-70G | 64 Kbit parallel EEPROM with 70 ns access, but uses different page write protocol and lacks toggle-bit detection | Requires modified driver code for write completion detection (DATA polling only); not drop-in software compatible | Choose only if migrating legacy designs and willing to adapt firmware for MXIC's timing model and feature set |
Compared with AT28HC64B-70JC, AT28C64B-70JC offers identical timing and footprint at lower cost but omits security-critical SDP and ID memory, while MX28LV640BTC-70G provides equivalent speed and density but demands firmware changes due to absence of toggle-bit support and differing page write constraints.
Availability
AT28HC64B-70JC is available at Aetrix Electronics and suitable for industrial automation, telecom infrastructure, and medical instrumentation requiring stable component supply, long-lifecycle support, and RoHS-compliant green packaging.
Supply support for AT28HC64B-70JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and manufacturing continuity for the AT28HC64B family.
The AT28HC64B series was designed as a high-reliability, pin-compatible upgrade to industry-standard 28-series EEPROMs, targeting legacy system modernization and long-life industrial deployments where data integrity and timing predictability are critical.
FAQ
What is the maximum page write size supported by the AT28HC64B-70JC?
The AT28HC64B-70JC supports a maximum page write size of 64 bytes. This is enabled by its internal 64-byte page register, which latches address and data during a single write cycle. All bytes written in one page operation must reside on the same page, defined by address bits A6–A12. The AT28HC64B-70JC requires each successive byte to be loaded within 150 µs (tBLC) of the previous byte to maintain page write mode.
Does the AT28HC64B-70JC require a 12 V programming voltage?
No, the AT28HC64B-70JC operates exclusively from a single 5 V ±10% supply for normal read/write operations. A 12 V ±0.5 V voltage applied to pin A9 is required only for accessing the extra 64-byte device identification area (addresses 1FC0H–1FFFH); it is not needed for standard memory operations. All other functions - including page write, DATA polling, and software data protection - operate at 5 V.
How does software data protection (SDP) work on the AT28HC64B-70JC?
Software data protection on the AT28HC64B-70JC is activated by writing a specific 3-byte command sequence (AAh → 55h → A0h) to addresses 1555h, 0AAAh, and 1555h respectively. Once enabled, all subsequent writes require repeating this sequence before data. The AT28HC64B-70JC retains SDP state across power cycles. Disabling SDP uses a separate 5-byte sequence (AAh → 55h → 80h → AAh → 20h), also written to the same addresses.
Can the AT28HC64B-70JC be used in place of a standard SRAM for read operations?
Yes, the AT28HC64B-70JC is accessed like a Static RAM for read cycles: with CE and OE low and WE high, data appears on I/O0–I/O7 within 70 ns. Its outputs go high-impedance when CE or OE is high, preventing bus contention. However, unlike SRAM, it does not support true random write without erase - write operations are slower (ms-scale) and wear-limited, so it must be used as nonvolatile storage, not volatile working memory.
What package type is used for the AT28HC64B-70JC?
The AT28HC64B-70JC uses a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package, designated as "32J" in Atmel's ordering nomenclature. It conforms to JEDEC MS-016, Variation AE, with pin 1 identified by a corner chamfer. Pins 1 and 17 are no-connect (NC) and must remain unconnected on the PCB. This surface-mount package supports reflow soldering and offers robust mechanical stability for industrial environments.
AT28HC64B-70JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 70 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28HC64B-70JC FAQ
1.How can I place an order for AT28HC64B-70JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-70JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-70JC reliable?
The price and inventory of AT28HC64B-70JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-70JC is usually 5 days.
3.What payment methods are accepted for AT28HC64B-70JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-70JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64B-70JC?
AT28HC64B-70JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-70JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-70JC?
For technical support, including AT28HC64B-70JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-70JC requirements.
6.How does Aetrix verify that AT28HC64B-70JC is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-70JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-70JC meets industry standards.
7.What is the process for return or replacement of AT28HC64B-70JC?
All AT28HC64B-70JC units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-70JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-70JC part is unused and in its original packaging.
Return procedure for AT28HC64B-70JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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