Microchip Technology AT28HC64B-70SI
- Part No.:
- AT28HC64B-70SI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28HC64B-70SI.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,286
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Product details
Overview
AT28HC64B-70SI from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with 70 ns read access time, JEDEC-standard byte-wide pinout, and industrial temperature range (−40°C to +85°C). It supports hardware/software data protection, DATA polling and toggle-bit write completion detection, and 1–64-byte page writes. Used in embedded systems for firmware storage, calibration data retention, and configuration memory where nonvolatile, byte-erasable, and SRAM-like interface are required.
For engineers reviewing the AT28HC64B-70SI datasheet, AT28HC64B-70SI pinout, AT28HC64B-70SI application, or AT28HC64B-70SI equivalent, key selection considerations include 5 V ±10% single-supply operation, CMOS/TTL compatibility, 100,000 write endurance, 10-year data retention, and support for both byte and page write modes with automatic internal timing.
Technical Context
The AT28HC64B-70SI implements a parallel EEPROM architecture with an 8-bit bidirectional I/O bus and 13-bit address bus (A0–A12), enabling direct replacement of static RAM in legacy designs without external logic. Its internal 64-byte page register latches addresses and data during page writes, freeing the bus for concurrent operations.
Write completion is verified via dual methods: DATA polling on I/O7 (complement-to-data during write, true data after completion) and toggle-bit behavior on I/O6 (toggling until write ends). Hardware protection includes VCC sense (<3.8 V inhibits writes), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable nonvolatile storage |
| Read Access Time | 70 ns - enables direct substitution for 70 ns SRAM in timing-critical control systems |
| Page Write Cycle | 10 ms max - allows burst programming of up to 64 bytes with single command initiation |
| Endurance | 100,000 write/erase cycles - suitable for field-updatable calibration tables with frequent rewrites |
| Data Retention | 10 years at 85°C - ensures long-term reliability in unattended industrial equipment |
| Supply Voltage | 5 V ±10% - compatible with standard TTL/CMOS logic rails without regulation overhead |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade embedded applications |
Pinout & Package
AT28HC64B-70SI is supplied in a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC) package per JEDEC MS-013, with lead pitch of 1.27 mm and body dimensions 17.70 × 7.40 × 2.35 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface supporting read, byte write, and page write operations |
| CE | Chip Enable | Active-low chip select; disables device and forces outputs to high-Z when high |
| OE | Output Enable | Active-low output control; enables data output only when CE is also low |
| WE | Write Enable | Active-low write strobe; initiates byte or page write on falling edge |
| GND / VCC | Power Terminals | Ground reference and 5 V supply; decoupling required within 1 cm of pins |
| NC | No Connect | Unbonded pin; must remain unconnected per datasheet (pins 1, 17 in SOIC variant) |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-wide Pinout | Direct drop-in replacement for industry-standard 28-pin parallel EEPROMs and SRAMs |
| Software Data Protection (SDP) | User-configurable write lock requiring 3-byte unlock sequence before any write operation |
| Hardware Write Inhibit | VCC sense, 5 ms power-on delay, and 15 ns noise filtering prevent spurious writes during power transitions |
| Page Write with Auto-Latching | Internal 64-byte register captures address/data, freeing bus for other tasks during 10 ms internal programming |
| Dual Write Completion Detection | Simultaneous DATA polling (I/O7) and toggle-bit (I/O6) allow flexible, interrupt-driven or polling-based firmware control |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Memory |
|---|---|
Use Scenario: Storing user-adjusted setpoints, alarm thresholds, and I/O mapping in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing SRAM-compatible read/write interface with guaranteed data retention across power cycles. Use Value: Eliminates battery-backed SRAM; 100,000-cycle endurance supports daily recalibration without wear-out concerns. | Use Scenario: Retaining sensor calibration coefficients and patient-specific therapy parameters in portable infusion pumps and diagnostic monitors. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter store accessed during boot and runtime via parallel bus. Use Value: Software data protection prevents accidental overwrite during firmware updates; 10-year retention meets medical device shelf-life requirements. |
| Automotive ECU Bootloader Metadata | Telecom Base Station Firmware Patch Storage |
Use Scenario: Holding bootloader version, secure boot flags, and flash update status in engine control units operating under extended temperature stress. IC Role / Device Role / Timing Role: Critical metadata repository interfaced directly to microcontroller's external memory bus. Use Value: −40°C to +85°C rating ensures reliability in under-hood environments; 70 ns access avoids CPU wait states. | Use Scenario: Storing hot-swappable firmware patches and configuration deltas in carrier-grade base station radios requiring zero-downtime updates. IC Role / Device Role / Timing Role: High-reliability patch staging area supporting atomic page-write updates with verification feedback. Use Value: Page write + DATA polling enables deterministic 10 ms update latency; 64-byte granularity minimizes bus occupancy during patch application. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECB90N6 | 64 Mbit density, 90 ns access, 3.3 V supply - not voltage- or pin-compatible | Targeted at higher-density, lower-voltage systems; requires level-shifting and PCB redesign | Select only if migrating to 3.3 V architecture and needing >64 Kbit capacity |
| Microchip 28C64B-25/P | Same 64 Kbit size, 250 ns access, PDIP package - slower timing, different package footprint | Suitable for cost-sensitive, non-speed-critical legacy designs with through-hole assembly | Choose for prototyping or low-volume production where 70 ns timing is not required |
Compared with ST M28W640ECB90N6 and Microchip 28C64B-25/P, the AT28HC64B-70SI uniquely delivers 70 ns speed, 5 V operation, SOIC packaging, and integrated software/hardware write protection in a JEDEC-standard 28-pin footprint - making it optimal for industrial upgrades requiring minimal layout change and robust data integrity.
Availability
AT28HC64B-70SI is available at Aetrix Electronics and suitable for industrial PLCs, medical calibration systems, automotive ECUs, and telecom base stations requiring stable component supply, long-lifecycle support, and green (Pb/Halide-free) packaging compliance.
Supply support for AT28HC64B-70SI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial, automotive, and consumer applications.
The AT28HC64B product line was designed for embedded systems requiring reliable, SRAM-compatible parallel EEPROM with fast access, page-write efficiency, and multi-layer data protection - targeting legacy design refreshes and cost-sensitive industrial upgrades.
FAQ
What is the maximum page write cycle time for AT28HC64B-70SI?
The AT28HC64B-70SI has a maximum page write cycle time of 10 ms under standard conditions. This value is specified in the AC characteristics table and applies to all variants of the AT28HC64B-70 speed grade, including the -70SI SOIC package. The 2 ms option referenced in some documentation applies only to the AT28HC64BF variant and is not valid for the AT28HC64B-70SI.
Does AT28HC64B-70SI support both hardware and software write protection?
Yes, AT28HC64B-70SI implements dual-layer write protection. Hardware protection includes VCC sensing (<3.8 V inhibits writes), 5 ms power-on delay, and 15 ns input noise filtering. Software Data Protection (SDP) is enabled via a three-byte unlock sequence written to specific addresses; once activated, SDP remains active across power cycles until explicitly disabled using a separate command sequence.
Can AT28HC64B-70SI be used as a direct replacement for standard SRAM in existing designs?
Yes, AT28HC64B-70SI is designed for SRAM-like interface compatibility: it uses identical read timing (CE/OE/WE control), JEDEC-standard pinout, and CMOS/TTL-level I/O. However, write operations require explicit timing management (DATA polling or toggle-bit monitoring), and write cycles take milliseconds - unlike SRAM's nanosecond writes - so firmware must accommodate this difference.
What package type is used for AT28HC64B-70SI?
AT28HC64B-70SI uses a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC) package, designated as "28S" in Atmel's ordering nomenclature. Its dimensions are 17.70 mm × 7.40 mm × 2.35 mm, with 1.27 mm lead pitch, and it complies with JEDEC MS-013 standards.
How does write completion detection work on AT28HC64B-70SI?
AT28HC64B-70SI provides two independent write completion detection methods: DATA polling monitors I/O7, which outputs the complement of the last written byte during programming and true data upon completion; toggle-bit detection monitors I/O6, which toggles between 0 and 1 during the write and stabilizes when complete. Both methods allow real-time status checking without halting system operation.
AT28HC64B-70SI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 70 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28HC64B-70SI FAQ
1.How can I place an order for AT28HC64B-70SI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-70SI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-70SI reliable?
The price and inventory of AT28HC64B-70SI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-70SI is usually 5 days.
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AT28HC64B-70SI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-70SI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-70SI?
For technical support, including AT28HC64B-70SI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-70SI requirements.
6.How does Aetrix verify that AT28HC64B-70SI is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-70SI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-70SI meets industry standards.
7.What is the process for return or replacement of AT28HC64B-70SI?
All AT28HC64B-70SI units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-70SI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-70SI part is unused and in its original packaging.
Return procedure for AT28HC64B-70SI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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