Microchip Technology AT28HC64B-70SU

Overview

AT28HC64B-70SU from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 70 ns read access time, hardware/software data protection, and page write capability supporting up to 64-byte writes in ≤10 ms. It operates from a single 5 V ±10% supply and targets firmware storage, configuration memory, and calibration data retention in industrial control modules.

For engineers reviewing the AT28HC64B-70SU datasheet, AT28HC64B-70SU pinout, AT28HC64B-70SU application, or AT28HC64B-70SU equivalent, key selection criteria include verified 70 ns read timing, CMOS/TTL-compatible I/O, 100 µA standby current, page-write endurance (100,000 cycles), and software data protection enable/disable command sequences.

Technical Context

The AT28HC64B-70SU implements a parallel interface with independent CE/OE/WE control logic enabling SRAM-like read/write operation without external timing circuitry. Its internal 64-byte page register latches address and data during page write, freeing the bus for concurrent operations.

Write completion detection uses dual methods: DATA Polling (I/O7 complement toggle) and Toggle Bit (I/O6 state alternation), both functional across full industrial temperature range (–40°C to +85°C). Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs.

Key Specifications

Pinout & Package

AT28HC64B-70SU is packaged in a 28-lead SOIC (0.300" wide, package code 28S), JEDEC MS-013 compliant, with 1.27 mm pitch gull-wing leads. Pin 1 identifier located at top-left corner per standard SOIC marking convention.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28HC64B-70JU, the AT28HC64B-70SU offers smaller PCB footprint and lower assembly cost; versus AT28HC256-70PU, it provides optimal cost/performance balance for sub-128 Kbit storage needs without over-provisioning memory.

Availability

AT28HC64B-70SU is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, automotive body electronics, and test equipment requiring stable component supply across extended product lifecycles.

Supply support for AT28HC64B-70SU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology acquired Atmel in 2016 and maintains full support for the AT28HC64B family, including datasheets, application notes, and long-term supply commitments.

The AT28HC64B series was designed as a drop-in SRAM-replacement EEPROM for legacy 5 V systems requiring reliable, low-power nonvolatile storage with parallel bus simplicity and robust write protection.

FAQ

What is the maximum page write size supported by the AT28HC64B-70SU?

The AT28HC64B-70SU supports page write operations of 1 to 64 bytes per internal programming cycle. All bytes must reside on the same page defined by address bits A6–A12, and successive bytes must be loaded within 150 µs (tBLC) of each other. This capability reduces firmware update time significantly compared to byte-by-byte writes, and is fully implemented in the AT28HC64B-70SU silicon.

Does the AT28HC64B-70SU require a 12 V supply for normal operation?

No, the AT28HC64B-70SU operates from a single 5 V ±10% supply for all standard read and write functions. A 12 V ±0.5 V supply on pin A9 is required only for accessing the dedicated 64-byte device identification area (addresses 1FC0H–1FFFH); this is an optional feature not needed for basic memory operation. The AT28HC64B-70SU remains fully functional at 5 V for all primary use cases.

How does software data protection work on the AT28HC64B-70SU?

Software data protection on the AT28HC64B-70SU is enabled by writing three specific bytes (AAh to address 1555h, 55h to address 0AAAh, then A0h to address 1555h) in sequence. Once activated, subsequent writes require repeating this unlock sequence before data can be written. The AT28HC64B-70SU ships with SDP disabled, and the feature remains active through power cycles until explicitly disabled using the defined disable command sequence.

Can the AT28HC64B-70SU be used as a direct replacement for SRAM in existing designs?

Yes, the AT28HC64B-70SU is designed for SRAM-compatible operation: it uses identical read timing (70 ns), JEDEC-standard byte-wide pinout, and requires no external components for read access. During writes, the internal timer handles programming automatically. However, write cycles take up to 10 ms, so the host must use DATA Polling or Toggle Bit to detect completion - unlike SRAM, which has no write latency. This behavior is fully documented for the AT28HC64B-70SU.

What is the purpose of the NC pins on the AT28HC64B-70SU SOIC package?

The AT28HC64B-70SU in 28-lead SOIC has two NC (No Connect) pins: pin 1 and pin 14. These pins are internally unconnected and must remain electrically floating or be tied to ground per PCB layout best practices to avoid noise coupling. They serve no functional role in memory operation, timing, or protection circuits, and their presence is due to package pinout standardization across the AT28HC64B family variants - including the AT28HC64B-70SU.