Microchip Technology AT28HC64B-70SU-T
- Part No.:
- AT28HC64B-70SU-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28HC64B-70SU-T.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28HC64B-70SU-T from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 70 ns read access time, hardware/software data protection, and page write capability supporting up to 64-byte writes in ≤10 ms. It operates on single 5 V ±10% supply and targets firmware storage, configuration memory, and calibration data retention in industrial control systems.
For engineers reviewing the AT28HC64B-70SU-T datasheet, AT28HC64B-70SU-T pinout, AT28HC64B-70SU-T application, or AT28HC64B-70SU-T equivalent, key selection criteria include verified 70 ns tACC timing, CMOS/TTL-compatible I/O, industrial temperature range (–40°C to +85°C), green SOIC-28 packaging, and support for DATA polling and toggle-bit write completion detection.
Technical Context
The AT28HC64B-70SU-T implements a parallel interface with static RAM-like read/write access-no external timing components required. Its internal 64-byte page register latches address and data during page write, enabling bus release after initiation while internal logic manages autonomous programming.
Write completion is confirmed via dual methods: DATA polling (I/O7 complement inversion) and toggle-bit detection (I/O6 toggling), both usable at any point during tWC. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, noise filtering (<15 ns pulses rejected), and CE/OE/WE state-dependent write inhibition.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable nonvolatile storage |
| Read Access Time | 70 ns maximum (tACC), enabling direct replacement of SRAM in legacy 5 MHz bus systems |
| Page Write Cycle | ≤10 ms max (standard), supports burst loading of 1–64 bytes within same A6–A12 page boundary |
| Supply Voltage | 5 V ±10%, compatible with standard TTL/CMOS logic rails without regulation overhead |
| Standby Current | 100 µA (CMOS mode), minimizing power in sleep states of battery-backed controllers |
| Endurance & Retention | 100,000 write/erase cycles and 10-year data retention at 85°C case temperature |
| Operating Temperature | –40°C to +85°C (industrial grade), validated across full voltage and timing margins |
Pinout & Package
AT28HC64B-70SU-T is packaged in a 28-lead, 0.300" wide plastic gull-wing small outline integrated circuit (SOIC-28), JEDEC MS-013 compliant, Pb/halide-free (green package).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 byte locations; A6–A12 define 64-byte page boundaries for write operations |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path for read/write; I/O7 used for DATA polling, I/O6 for toggle-bit detection |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; inhibits writes when high |
| OE | Output Enable | Active-low output control; places I/O pins in high-Z when high, preventing bus contention |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; write inhibited if held high |
| VCC, GND | Power Supply | Single 5 V ±10% supply; no separate VPP required-programming uses internal charge pump |
| NC | No Connect | Pins 1 and 28 are unconnected; must remain floating per datasheet layout guidance |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Architecture | Internal 64-byte latch enables burst writes without CPU bus occupation beyond initial setup |
| Dual Write Completion Detection | Hardware-supported DATA polling (I/O7) and toggle-bit (I/O6) allow flexible, non-blocking firmware polling loops |
| Software Data Protection (SDP) | User-configurable 3-byte unlock sequence prevents accidental writes while permitting intentional updates |
| Hardware Write Inhibit | VCC sense, 5 ms power-up delay, and noise filtering eliminate spurious writes during power transients |
| Extended Identification Area | Dedicated 64-byte EEPROM region (1FC0H–1FFFH) accessible via 12 V on A9 for device serialization or calibration storage |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Memory |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing deterministic boot-time parameter recovery after power loss. Use Value: 100,000-cycle endurance and 10-year data retention ensure reliability over multi-year maintenance intervals without backup batteries. | Use Scenario: Retaining sensor calibration coefficients, user preferences, and regulatory audit logs in portable diagnostic equipment operating across temperature extremes. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter store interfaced directly to microcontroller address/data bus. Use Value: Software Data Protection (SDP) prevents unintended overwrites during firmware updates or field service, meeting IEC 62304 software safety requirements. |
| Automotive Body Control Module (BCM) | Telecom Base Station Settings Memory |
Use Scenario: Holding seat/mirror position presets, lighting profiles, and door lock configurations in automotive BCMs where EEPROM must survive cold-cranking voltage dips. IC Role / Device Role / Timing Role: Directly mapped parallel memory accessed via MCU's external bus interface during system initialization. Use Value: Hardware write inhibit (VCC < 3.8 V lockout) ensures zero inadvertent writes during 4.5–5.5 V brownout conditions typical in vehicle electrical systems. | Use Scenario: Preserving RF channel assignments, gain settings, and network registration keys in outdoor telecom base stations exposed to wide thermal cycling. IC Role / Device Role / Timing Role: Industrial-grade nonvolatile memory co-located with baseband processor for fast, deterministic configuration reload. Use Value: –40°C to +85°C operation and 70 ns tACC enable real-time parameter access without wait states in time-sensitive radio control paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECT | 64 Mbit density (8M × 8), 120 ns access, requires VPP = 12 V for write; no built-in page latch | Higher density but slower and less bus-friendly; lacks SDP and toggle-bit detection | Choose only when >64 Kbit capacity is mandatory and timing budget allows ≥120 ns reads |
| Microchip 25LC640A-I/SN | 64 Kbit SPI interface, 5 MHz clock, 5 ms page write; no parallel bus, no hardware write inhibit | Requires serial protocol stack and GPIO bit-banging; unsuitable for SRAM-drop-in replacement | Select only for space-constrained designs accepting SPI overhead and sacrificing deterministic timing |
Compared with ST M28W640ECT and Microchip 25LC640A-I/SN, the AT28HC64B-70SU-T delivers optimal balance of speed (70 ns), ease of integration (JEDEC byte-wide pinout), and robustness (dual write detection + hardware/software protection) for legacy parallel bus systems requiring field-proven reliability.
Availability
AT28HC64B-70SU-T is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, automotive body control modules, telecom infrastructure, and embedded instrumentation requiring stable component supply with long-term lifecycle assurance.
Supply support for AT28HC64B-70SU-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial, automotive, and consumer applications.
The AT28HC64B product line was designed as a drop-in parallel EEPROM replacement for SRAM-based systems needing nonvolatile configuration storage with minimal design change-emphasizing timing compatibility, bus simplicity, and field reliability.
FAQ
What is the maximum page write size supported by the AT28HC64B-70SU-T?
The AT28HC64B-70SU-T supports page write operations of 1 to 64 bytes per cycle. All bytes must reside within the same 64-byte page defined by address bits A6–A12, and each subsequent byte must be loaded within 150 µs (tBLC) of the prior one. The internal page register latches the entire block, enabling autonomous programming without further CPU intervention after initiation. This capability is confirmed in the AT28HC64B-70SU-T datasheet Section 4.3 and AC Characteristics Table 16.
Does the AT28HC64B-70SU-T require an external high-voltage supply for programming?
No, the AT28HC64B-70SU-T does not require an external high-voltage supply for standard write operations. It operates from a single 5 V ±10% supply and uses an internal charge pump for programming. Only the optional device identification area (1FC0H–1FFFH) requires 12 V ±0.5 V applied to pin A9-this is strictly for writing to the extra 64-byte ID sector and is not needed for normal memory operation. All standard reads and writes function fully at 5 V.
How does hardware write protection work on the AT28HC64B-70SU-T?
Hardware write protection on the AT28HC64B-70SU-T comprises four mechanisms: (1) VCC sense disables writes if supply drops below ~3.8 V; (2) a 5 ms internal timer prevents writes until VCC stabilizes post-power-up; (3) write is inhibited if CE is high, OE is low, or WE is high; and (4) input noise filter rejects pulses <15 ns on CE/WE. These features are active at all times and require no firmware configuration-ensuring immunity to power glitches and signal noise during critical system transitions.
Can the AT28HC64B-70SU-T be used as a direct replacement for SRAM in existing designs?
Yes, the AT28HC64B-70SU-T is explicitly designed for SRAM-drop-in replacement. Its JEDEC-standard byte-wide pinout, 70 ns read access time, and identical read cycle timing (CE/OE/WE control) allow substitution without PCB changes. During reads, it behaves identically to static RAM-asserting data on I/O lines when CE and OE are low and WE is high. Write cycles differ only in timing and completion detection, making integration straightforward for legacy systems upgrading to nonvolatile storage.
What is the purpose of the extra 64 bytes of EEPROM in the AT28HC64B-70SU-T?
The AT28HC64B-70SU-T includes an additional 64 bytes of EEPROM (addresses 1FC0H–1FFFH) reserved for device identification, calibration data, or manufacturing traceability. Access requires applying 12 V ±0.5 V to pin A9 while performing standard read/write cycles. This dedicated region operates independently of main memory and retains data with the same 100,000-cycle endurance and 10-year retention-providing a secure, isolated storage zone for sensitive or infrequently updated information without consuming main array capacity.
AT28HC64B-70SU-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 70 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28HC64B-70SU-T FAQ
1.How can I place an order for AT28HC64B-70SU-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-70SU-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-70SU-T reliable?
The price and inventory of AT28HC64B-70SU-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-70SU-T is usually 5 days.
3.What payment methods are accepted for AT28HC64B-70SU-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-70SU-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64B-70SU-T?
AT28HC64B-70SU-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-70SU-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-70SU-T?
For technical support, including AT28HC64B-70SU-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-70SU-T requirements.
6.How does Aetrix verify that AT28HC64B-70SU-T is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-70SU-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-70SU-T meets industry standards.
7.What is the process for return or replacement of AT28HC64B-70SU-T?
All AT28HC64B-70SU-T units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-70SU-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-70SU-T part is unused and in its original packaging.
Return procedure for AT28HC64B-70SU-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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