Microchip Technology AT28HC64B-70TI

Overview

AT28HC64B-70TI from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 70 ns read access time, single 5 V ±10% supply, and industrial temperature range (–40°C to +85°C). It supports hardware/software data protection, DATA polling, and toggle-bit write completion detection for embedded firmware storage and configuration retention in microcontroller systems.

For engineers reviewing the AT28HC64B-70TI datasheet, AT28HC64B-70TI pinout, AT28HC64B-70TI application, or AT28HC64B-70TI equivalent, key selection criteria include page-write capability (1–64 bytes), CMOS/TTL compatibility, 100 µA standby current, 100,000 write endurance cycles, and green (Pb/halide-free) TSOP packaging.

Technical Context

The AT28HC64B-70TI implements a static RAM-compatible interface with dual-line chip enable (CE) and output enable (OE) control to prevent bus contention. Its internal 64-byte page register latches address and data during write operations, freeing the bus for concurrent system activity.

Write completion is verified via I/O7 DATA polling (complement-to-data behavior) or I/O6 toggle-bit detection-both operable at any point during tWC. Hardware write inhibition includes VCC sense (<3.8 V), 5 ms power-on delay, noise filtering (<15 ns pulses), and CE/OE/WE logic gating.

Key Specifications

Pinout & Package

AT28HC64B-70TI uses a 28-lead Plastic Thin Small Outline Package (TSOP), Type I (8 mm × 13.4 mm), compliant with JEDEC MO-183. Pin 1 identifier is marked on the package top surface.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28HC64B-70SI and AT28HC64B-70PI, the AT28HC64B-70TI offers the smallest footprint (TSOP) and best thermal performance for high-density PCBs, while maintaining identical functionality, timing, and endurance-making it optimal for volume production in space-constrained embedded systems.

Availability

AT28HC64B-70TI is available at Aetrix Electronics and suitable for industrial automation, medical diagnostics, automotive body electronics, and telecom infrastructure requiring stable component supply and long-term lifecycle support.

Supply support for AT28HC64B-70TI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.

The AT28HC64B product line delivers high-reliability parallel EEPROMs optimized for firmware storage, configuration retention, and calibration data logging in industrial, medical, and automotive systems.

FAQ

What is the maximum page write size supported by the AT28HC64B-70TI?

The AT28HC64B-70TI supports page write operations of 1 to 64 bytes per internal programming cycle. All bytes must reside on the same 64-byte page, defined by address bits A6–A12. The device internally latches addresses and data during the write sequence, enabling efficient bulk updates without host-side timing constraints beyond the 150 µs byte-load cycle (tBLC).

Does the AT28HC64B-70TI require external high-voltage circuitry for programming?

No, the AT28HC64B-70TI operates from a single 5 V ±10% supply and requires no external high-voltage programming circuitry. Chip erase and byte/page writes use standard logic-level signals. Only device identification memory (1FC0H–1FFFH) requires 12 V on A9, which is not used in normal operation of the AT28HC64B-70TI.

How does software data protection (SDP) function on the AT28HC64B-70TI?

SDP on the AT28HC64B-70TI is enabled by writing three specific bytes (AAh, 55h, A0h) to designated addresses (1555h, 0AAAh, 1555h). Once activated, all subsequent writes require repeating this sequence before data. SDP remains active across power cycles and protects against accidental writes during brownouts or resets-critical for safeguarding calibration data in the AT28HC64B-70TI.

Can the AT28HC64B-70TI be used as a direct replacement for SRAM in existing designs?

Yes-the AT28HC64B-70TI uses a static RAM-compatible interface: CE and OE control read access, WE controls writes, and outputs go high-Z when disabled. With 70 ns access time and TTL/CMOS compatibility, it replaces SRAM in read-dominant applications where nonvolatility is required, though write cycles require explicit polling or toggle-bit checking unlike SRAM's instantaneous writes.

What is the purpose of the NC pins on the AT28HC64B-70TI TSOP package?

The NC (No Connect) pins on the AT28HC64B-70TI TSOP package-specifically pins 3, 4, 27, and 28-are unconnected internally and must remain floating. They exist for mechanical symmetry and package standardization but carry no electrical function. Connecting them risks violating absolute maximum ratings or inducing noise; the AT28HC64B-70TI datasheet explicitly prohibits routing traces or applying voltage to these pins.