My Inquiry
My Account
Microchip Technology AT28HC64B-90JC
- Part No.:
- AT28HC64B-90JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28HC64B-90JC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:1,592
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC64B-90JC from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 90 ns read access time, 10 ms page write cycle, and hardware/software data protection. It operates from a single 5 V ±10% supply and supports commercial temperature range (0°C to 70°C), used in embedded system configuration storage and firmware parameter retention.
For engineers reviewing the AT28HC64B-90JC datasheet, AT28HC64B-90JC pinout, AT28HC64B-90JC application, or AT28HC64B-90JC equivalent, key selection considerations include its 64-byte page write capability, DATA polling/toggle bit write completion detection, CMOS/TTL compatibility, 100 µA standby current, and PLCC-32 packaging for through-hole mounting in industrial control modules.
Technical Context
The AT28HC64B-90JC implements a parallel interface with independent CE/OE/WE control logic enabling SRAM-like read/write cycles without external timing components. Its internal 64-byte page register latches address and data during page writes, freeing the bus for concurrent operations while an internal timer manages erase-and-program sequencing.
Write completion is verified via dual deterministic methods: DATA polling on I/O7 (complement-to-data during write, true data after completion) and toggle-bit behavior on I/O6 (repeated toggling until write ends). Hardware protection includes VCC sense (<3.8 V inhibits write), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), sufficient for boot configuration tables or calibration data sets in microcontroller-based systems |
| Read Access Time | 90 ns maximum - enables direct interfacing with 8-bit MCUs running at ≤10 MHz without wait states |
| Page Write Cycle | 10 ms maximum - allows efficient bulk updates of up to 64 bytes per operation, reducing host CPU overhead |
| Supply Voltage | 5 V ±10% - compatible with legacy 5 V logic families and eliminates need for level-shifting circuitry |
| Standby Current | 100 µA typical - supports low-power modes in battery-backed or energy-conscious applications |
| Data Retention | 10 years minimum - ensures long-term reliability for infrequently updated system parameters |
| Endurance | 100,000 write/erase cycles - suitable for field-updatable firmware metadata or logging counters |
Pinout & Package
AT28HC64B-90JC is packaged in a 32-lead Plastic J-Leaded Chip Carrier (PLCC), JEDEC MS-016 compliant, with 1.27 mm pitch and gull-wing leads. Pins 1 and 17 are No Connect (NC). The package supports reflow soldering and provides mechanical robustness for industrial environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface supporting byte or page reads/writes; TTL/CMOS compatible voltage levels |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read access; controls device activation |
| OE | Output Enable | Active-low output gate; places I/O pins in high-impedance state when high, preventing bus contention |
| WE | Write Enable | Active-low write strobe; initiates byte or page write on falling edge; combined with CE for dual-line write control |
| VCC / GND | Power Supply | Single 5 V ±10% supply with decoupling recommended; ground reference for all digital and analog functions |
| NC | No Connect | Pins 1 and 17 are unconnected internally - must remain floating or tied to ground per layout best practices |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte Page Write | Reduces host-side write overhead by up to 64× versus byte-by-byte programming; requires no external address sequencing logic |
| DATA Polling & Toggle Bit | Enables deterministic, non-blocking write completion detection using only standard read cycles - no dedicated status registers needed |
| Hardware + Software Data Protection | VCC sensing, 5 ms power-on delay, and noise filtering prevent spurious writes; software protection (SDP) adds user-configurable lock/unlock via 3-byte command sequence |
| JEDEC Byte-wide Pinout | Ensures drop-in compatibility with legacy SRAM and EPROM sockets, simplifying board redesigns and second-source qualification |
| Industrial-Grade Reliability | 100,000 endurance cycles and 10-year data retention validated across 0°C to 70°C ambient - meets requirements for unattended equipment |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
|
Use Scenario: Storing I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers deployed in factory automation lines. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing persistent parameter storage between power cycles and firmware updates. Use Value: Enables field-reconfigurable operation without requiring battery backup or external NVRAM; 90 ns access supports real-time scan-cycle execution. |
Use Scenario: Retaining sensor calibration coefficients and patient-specific therapy settings in portable infusion pumps and diagnostic monitors. IC Role / Device Role / Timing Role: Secure parameter vault with hardware write inhibit and software protection to prevent accidental overwrite during service mode. Use Value: Meets IEC 62304 safety requirements for data integrity; 100 µA standby current extends battery life in handheld devices. |
| Telecom Line Card Boot Parameters | Automotive Body Control Module Settings |
|
Use Scenario: Holding MAC addresses, port assignments, and firmware version stamps in carrier-grade DSLAM line cards operating continuously for years. IC Role / Device Role / Timing Role: Factory-programmed identity and initialization store accessed during cold boot before FPGA or DSP initialization. Use Value: JEDEC pinout allows reuse of existing PCB footprints; 10-year data retention eliminates periodic recalibration maintenance. |
Use Scenario: Saving user preferences (window position, mirror angle, lighting profiles) and fault history logs in automotive BCMs subjected to thermal cycling. IC Role / Device Role / Timing Role: Robust nonvolatile scratchpad memory tolerant of automotive voltage transients and extended temperature exposure. Use Value: Hardware VCC-sense protection prevents corruption during ignition transients; 100,000-cycle endurance supports lifetime vehicle usage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECT | 64 Mbit density, 110 ns access, 3.3 V core with 5 V I/O tolerance; lacks software data protection | Higher density for firmware image storage; not suitable for 5 V-only systems without level shifters | Select when migrating to higher-density parallel EEPROM with mixed-voltage support and no SDP requirement |
| ON Semiconductor CAT28C64B | Identical 64 Kbit organization and 90 ns speed; same PLCC-32 package; 100 µA standby current; no 12 V A9 programming for ID area | Drop-in replacement for AT28HC64B-90JC in most designs; lacks extended device identification EEPROM (1FC0H–1FFFH) | Preferred for cost-sensitive industrial designs where device ID tracking is unnecessary and second-source assurance is required |
Compared with ST M28W640ECT and CAT28C64B, the AT28HC64B-90JC offers unique software data protection and 64-byte device ID space, making it optimal for applications requiring field-programmable security and traceability without increasing footprint or voltage complexity.
Availability
AT28HC64B-90JC is available at Aetrix Electronics and suitable for industrial PLCs, medical instrumentation, telecom line cards, and automotive body control modules requiring stable component supply, long-lifecycle support, and RoHS-compliant green packaging.
Supply support for AT28HC64B-90JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and manufacturing continuity for the AT28HC64B family.
The AT28HC64B series was designed as a pin-compatible, enhanced-reliability successor to industry-standard 28C64 EEPROMs, targeting applications needing deterministic write verification, low-power standby, and robust data protection in harsh environments.
FAQ
What is the maximum page write cycle time for AT28HC64B-90JC?
The AT28HC64B-90JC has a maximum page write cycle time of 10 ms under standard conditions. An optional 2 ms version exists but requires special ordering (e.g., AT28HC64B-90JU with green packaging); the AT28HC64B-90JC itself is rated at 10 ms. This timing is internally controlled and does not require external clocking or handshaking signals.
Does AT28HC64B-90JC support both hardware and software write protection?
Yes, AT28HC64B-90JC implements dual-layer protection: hardware features include VCC sensing (<3.8 V disables writes), 5 ms power-on delay, and 15 ns noise filtering on WE/CE inputs; software data protection (SDP) is enabled/disabled via a documented 3-byte command sequence written to specific addresses (1555H, 0AAAH, then 1555H), and remains active across power cycles.
Can AT28HC64B-90JC be used as a direct replacement for older 28C64 EEPROMs?
Yes, AT28HC64B-90JC uses JEDEC-approved byte-wide pinout and matches the 28C64's 28-pin DIP/SOIC footprint in compatible variants, but the AT28HC64B-90JC is specifically packaged in 32-lead PLCC. For true drop-in replacement, verify package type: AT28HC64B-90PC (PDIP) or AT28HC64B-90SC (SOIC) would match legacy footprints, whereas AT28HC64B-90JC requires PLCC socket compatibility.
How is write completion detected on AT28HC64B-90JC?
AT28HC64B-90JC provides two independent, deterministic methods: DATA polling reads I/O7 - it outputs the complement of the last written byte during programming and true data upon completion; toggle bit monitoring reads I/O6 - it toggles between 0 and 1 during write and stabilizes when complete. Both methods work at any time during the write cycle and require no additional hardware.
What is the purpose of the extra 64 bytes of EEPROM in AT28HC64B-90JC?
The AT28HC64B-90JC includes 64 bytes of dedicated device identification EEPROM (addresses 1FC0H–1FFFH), accessible by raising A9 to 12 V ±0.5 V. This space is used for storing unique serial numbers, calibration data, manufacturing lot codes, or firmware revision stamps - separate from main memory and immune to standard write commands unless explicitly addressed with elevated voltage.
AT28HC64B-90JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28HC64B-90JC FAQ
1.How can I place an order for AT28HC64B-90JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-90JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-90JC reliable?
The price and inventory of AT28HC64B-90JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-90JC is usually 5 days.
3.What payment methods are accepted for AT28HC64B-90JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-90JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64B-90JC?
AT28HC64B-90JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-90JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-90JC?
For technical support, including AT28HC64B-90JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-90JC requirements.
6.How does Aetrix verify that AT28HC64B-90JC is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-90JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-90JC meets industry standards.
7.What is the process for return or replacement of AT28HC64B-90JC?
All AT28HC64B-90JC units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-90JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-90JC part is unused and in its original packaging.
Return procedure for AT28HC64B-90JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC64B-90JC Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
