My Inquiry
My Account
Microchip Technology AT28HC64B-90PC
- Part No.:
- AT28HC64B-90PC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
AT28HC64B-90PC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28DIP
- Quantity:
- Payment:
- Shipping:
Inventory:4,833
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28HC64B-90PC from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 90 ns read access time, 10 ms page write cycle, and CMOS/TTL-compatible I/O. It operates from a single 5 V ±10% supply and supports hardware/software data protection for embedded configuration storage in industrial controllers.
For engineers reviewing the AT28HC64B-90PC datasheet, AT28HC64B-90PC pinout, AT28HC64B-90PC application, or AT28HC64B-90PC equivalent, this page delivers verified timing specs, page-write behavior, DATA polling/toggle-bit write completion detection, and industrial-grade (-40°C to +85°C) operation in 28-lead PDIP packaging.
Technical Context
The AT28HC64B-90PC implements a static RAM-like interface with dual-line chip enable (CE) and output enable (OE) control to prevent bus contention. Its internal 64-byte page register latches addresses and data during page writes, freeing the bus for concurrent operations.
Write completion is confirmed via two independent methods: DATA polling on I/O7 (complement-to-data during write, true data after completion) and toggle-bit detection on I/O6 (toggling until write ends). Hardware protection includes VCC sense (<3.8 V inhibits write), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits); sufficient for firmware parameter tables or calibration data in microcontroller-based systems. |
| Read Access Time | 90 ns maximum; enables direct replacement of SRAM in legacy 8-bit bus systems without timing redesign. |
| Page Write Cycle | 10 ms maximum (standard); allows burst programming of up to 64 bytes per cycle, reducing host CPU overhead vs. byte-by-byte writes. |
| VCC Supply | Single 5 V ±10%; eliminates need for auxiliary voltage rails in 5 V logic environments. |
| Standby Current | 100 µA CMOS; supports low-power modes in battery-backed or energy-constrained applications. |
| Data Retention | 10 years minimum; ensures long-term reliability for infrequently updated configuration storage. |
| Endurance | 100,000 write/erase cycles; suitable for field-updatable parameters with moderate update frequency. |
Pinout & Package
AT28HC64B-90PC is supplied in a 28-lead plastic dual-inline package (PDIP), 0.600" wide (28P6), with JEDEC-standard byte-wide pinout and no internal connections on pins 1 and 28 (NC).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte page writes. |
| I/O0–I/O7 | Bidirectional Data Bus | Byte-wide parallel interface compatible with 8-bit microcontrollers and FPGA glue logic; supports read, byte write, and page write. |
| CE | Chip Enable | Active-low global enable; must be low for any access; combined with OE/WE to determine read/write mode per JEDEC timing. |
| OE | Output Enable | Active-low control for output drivers; high during writes, low during reads; enables bus sharing with other peripherals. |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; used with CE for byte or page write initiation per AC waveforms. |
| GND / VCC | Power Terminals | Ground reference and 5 V supply; decoupling capacitor required near VCC pin to maintain stable operation during page write current spikes. |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte Page Write | Reduces host processor intervention by enabling sequential 1–64 byte writes within a single 10 ms internal cycle, improving system throughput. |
| DATA Polling (I/O7) | Allows real-time write status monitoring without dedicated status lines-read last written byte returns complement until completion, then true data. |
| Toggle Bit (I/O6) | Provides asynchronous write completion detection: I/O6 toggles at ~1 MHz during write, stops when complete-no address dependency. |
| Software Data Protection | User-configurable 3-byte command sequence (AAh/55h/A0h) enables/disables write lock, preventing accidental overwrites during power transitions. |
| Hardware Write Inhibit | VCC sense, 5 ms power-on delay, and 15 ns noise filtering on WE/CE ensure immunity to brown-out and EMI-induced spurious writes. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
|
Use Scenario: Storing sensor calibration coefficients and operational thresholds in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during boot and runtime; 90 ns read speed ensures minimal impact on scan cycle timing. Use Value: 100,000 endurance cycles support field recalibration; industrial temperature range (-40°C to +85°C) guarantees reliability in uncontrolled cabinet environments. |
Use Scenario: Retaining patient-specific therapy parameters and device serial tracking data in portable diagnostic instruments with battery backup. IC Role / Device Role / Timing Role: Secure parameter store with software/hardware write protection; 10-year data retention meets regulatory requirements for medical records. Use Value: 100 µA standby current extends battery life; page write reduces host MCU wake time during parameter updates. |
| Automotive Body Control Module | Telecom Equipment Bootloader Settings |
|
Use Scenario: Holding door lock logic states, lighting profiles, and user preferences in automotive body control units subject to thermal cycling. IC Role / Device Role / Timing Role: EEPROM interfaced directly to 8-bit MCU bus; JEDEC pinout simplifies PCB layout reuse from legacy SRAM designs. Use Value: Green (Pb/Halide-free) PDIP package complies with automotive RoHS; hardware VCC sensing prevents corruption during ignition transients. |
Use Scenario: Storing bootloader version, network MAC address, and fail-safe recovery flags in carrier-grade DSLAMs and base station controllers. IC Role / Device Role / Timing Role: Critical nonvolatile storage accessed during power-up initialization; 5 V compatibility matches legacy telecom power architecture. Use Value: Dual write-detection methods (polling + toggle bit) enable robust firmware update verification; 64-byte page write accelerates field upgrade sequences. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M48T02-90PC1 | Real-time clock + 2 Kbit NV SRAM; no page write; 100 ns access; separate RTC battery input. | RTC-critical systems requiring time-stamped logs; not suitable for pure configuration storage without clock function. | Select when timekeeping is mandatory; avoid if only nonvolatile memory is needed due to higher cost and complexity. |
| ON Semiconductor CAT28C64B-90PC | Pin-compatible clone with identical 90 ns timing, 10 ms page write, and same PDIP-28 footprint; minor differences in DC leakage specs. | Drop-in replacement for AT28HC64B-90PC in existing designs; validated for same industrial temperature range. | Preferred for second-source assurance; verify SDP command sequence compatibility if software protection is enabled. |
Compared with ST M48T02-90PC1, AT28HC64B-90PC offers higher density and faster page writes but lacks RTC; versus CAT28C64B-90PC, it provides identical functionality with proven Atmel firmware ecosystem integration.
Availability
AT28HC64B-90PC is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, and automotive body control modules requiring stable component supply across extended product lifecycles.
Supply support for AT28HC64B-90PC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel parallel EEPROMs, including manufacturing, documentation, and technical resources.
The AT28HC64B product line was designed for reliable, pin-compatible replacement of battery-backed SRAM in industrial and automotive systems requiring field-updatable nonvolatile storage without external timing components.
FAQ
What is the maximum page write cycle time for AT28HC64B-90PC?
The AT28HC64B-90PC has a standard maximum page write cycle time of 10 ms. An optional 2 ms version exists (AT28HC64B-90PC-2MS), but the -90PC suffix denotes the standard 10 ms variant. This timing is internally controlled and does not require external clocks or handshaking signals.
Does AT28HC64B-90PC support both hardware and software write protection?
Yes, AT28HC64B-90PC implements dual-layer protection: hardware features include VCC sensing (<3.8 V disables writes), 5 ms power-on delay, and noise filtering on WE/CE inputs; software protection uses a three-byte command sequence (AAh/55h/A0h) to enable/disable write lock, shipped disabled from factory.
Can AT28HC64B-90PC be used as a direct replacement for SRAM in an existing design?
Yes, AT28HC64B-90PC uses JEDEC-standard byte-wide pinout and behaves like SRAM during reads (CE/OE low, WE high). However, write cycles require timing compliance (e.g., tWP ≥100 ns) and write completion detection (polling/toggle bit); unlike SRAM, it cannot be written continuously without verification.
What package type is used for AT28HC64B-90PC?
AT28HC64B-90PC is packaged in a 28-lead plastic dual-inline package (PDIP), 0.600" wide (28P6), with lead spacing of 2.54 mm (0.100"). Pins 1 and 28 are no-connect (NC), and the package meets JEDEC MS-011 standards.
How is write completion detected on AT28HC64B-90PC?
AT28HC64B-90PC provides two independent methods: DATA polling monitors I/O7 (returns complement of last written byte until completion, then true data), and the toggle bit monitors I/O6 (toggles between 0/1 during write, stops when complete). Both can be initiated at any time during the write cycle.
AT28HC64B-90PC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-DIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-PDIP
AT28HC64B-90PC FAQ
1.How can I place an order for AT28HC64B-90PC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-90PC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-90PC reliable?
The price and inventory of AT28HC64B-90PC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-90PC is usually 5 days.
3.What payment methods are accepted for AT28HC64B-90PC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-90PC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64B-90PC?
AT28HC64B-90PC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-90PC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-90PC?
For technical support, including AT28HC64B-90PC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-90PC requirements.
6.How does Aetrix verify that AT28HC64B-90PC is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-90PC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-90PC meets industry standards.
7.What is the process for return or replacement of AT28HC64B-90PC?
All AT28HC64B-90PC units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-90PC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-90PC part is unused and in its original packaging.
Return procedure for AT28HC64B-90PC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28HC64B-90PC Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
