Microchip Technology AT28HC64B-90PU
- Part No.:
- AT28HC64B-90PU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
AT28HC64B-90PU.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28DIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,220
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Product details
Overview
AT28HC64B-90PU from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 90 ns read access time, single 5 V ±10% supply operation, and hardware/software data protection - used in industrial control firmware storage, BIOS configuration backup, and embedded system parameter retention.
For engineers reviewing the AT28HC64B-90PU datasheet, AT28HC64B-90PU pinout, AT28HC64B-90PU application, or AT28HC64B-90PU equivalent, key selection criteria include page write capability (1–64 bytes), DATA polling/toggle bit write completion detection, CMOS/TTL compatibility, industrial temperature range (−40°C to +85°C), and green Pb/halide-free packaging.
Technical Context
The AT28HC64B-90PU implements a parallel interface with CE/OE/WE control logic enabling SRAM-like read/write cycles without external timing components. Its internal 64-byte page register latches address and data during page writes, freeing the bus for concurrent operations.
Write completion is verified via dual methods: DATA polling on I/O7 (complement-to-data during write, true data after completion) and toggle-bit behavior on I/O6. Hardware protection includes VCC sense (<3.8 V inhibits write), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits) - supports full firmware image or configuration table storage in space-constrained systems |
| Read Access Time | 90 ns maximum - enables direct replacement of faster SRAM in non-volatile boot code or lookup table applications |
| Page Write Cycle | 10 ms maximum - reduces firmware update latency vs. byte-by-byte programming; supports burst writes up to 64 bytes per cycle |
| Endurance | 100,000 write/erase cycles - suitable for field-upgradable devices requiring frequent parameter logging or calibration updates |
| Data Retention | 10 years at 85°C - guarantees long-term reliability in unattended industrial equipment and telecom infrastructure |
| Supply Voltage | 5 V ±10% - interoperable with legacy 5 V logic families without level-shifting circuitry |
| Standby Current | 100 µA CMOS - minimizes quiescent power in battery-backed or energy-sensitive applications |
Pinout & Package
AT28HC64B-90PU is supplied in a 28-lead PDIP (Plastic Dual Inline Package), 0.600" wide, with JEDEC-standard byte-wide pinout and NC (No Connect) pins at positions 1 and 14.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte page writes |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read access; inhibits all operations when high |
| OE | Output Enable | Active-low output control; places I/O0–I/O7 in high-impedance state when high to prevent bus contention |
| WE | Write Enable | Active-low write strobe; initiates byte or page write on falling edge; must be high during reads |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path for reading stored values or loading new data; supports DATA polling on I/O7 and toggle-bit detection on I/O6 |
| GND / VCC | Power Terminals | Ground reference and 5 V supply pins; decoupling capacitor placement near VCC/GND is critical for stable page write timing |
| NC | No Connect | Pins 1 and 14 are unconnected; must remain floating - no external biasing or routing permitted |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Operation | Enables 1–64-byte simultaneous writes with internal latching - eliminates host CPU wait states and improves firmware update throughput |
| DATA Polling & Toggle Bit | Dual asynchronous write completion detection - allows host to poll I/O7 or monitor I/O6 toggling without fixed timeout delays |
| Software Data Protection (SDP) | User-configurable write lock via 3-byte command sequence (AAh/55h/A0h) - prevents accidental overwrites during power transitions or debug sessions |
| Hardware Write Inhibit | VCC sense, 5 ms power-on delay, and noise filtering on WE/CE - ensures robustness against brown-out, ESD, and signal glitches |
| Device Identification Area | 64-byte dedicated EEPROM segment (1FC0H–1FFFH) accessible with 12 V on A9 - supports unique device serialization and traceability |
Applications
| Industrial PLC Configuration Storage | Embedded System Bootloader Parameter Backup |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and calibration coefficients in programmable logic controllers operating continuously in factory environments. IC Role / Device Role / Timing Role: Non-volatile configuration memory accessed during startup and runtime; retains settings across power cycles and hot-swaps. Use Value: 100,000 endurance cycles and 10-year data retention ensure reliable operation over 10+ years of industrial deployment without maintenance. |
Use Scenario: Preserving bootloader version, secure boot keys, and hardware revision flags in network routers and gateways requiring field firmware upgrades. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to microcontroller's external memory bus; provides fast 90 ns read access for boot-time initialization. Use Value: Page write capability reduces firmware patch time by >95% compared to byte-write-only alternatives, accelerating over-the-air update rollouts. |
| Medical Device Calibration Data Archive | Automotive Body Control Module Settings |
Use Scenario: Archiving sensor offset corrections, gain adjustments, and diagnostic history logs in portable ultrasound and infusion pumps subject to strict regulatory traceability requirements. IC Role / Device Role / Timing Role: Secure, tamper-resistant memory with SDP enabled; identification area stores manufacturing lot and calibration timestamp. Use Value: Hardware write inhibit and 12 V–enabled ID sector meet IEC 62304 software lifecycle requirements for Class C medical devices. |
Use Scenario: Storing seat position presets, mirror angle configurations, and lighting profiles in automotive body control modules (BCM) with CAN-based user interfaces. IC Role / Device Role / Timing Role: Low-power (100 µA standby) non-volatile memory interfaced to 5 V MCU peripherals; survives vehicle battery disconnect events. Use Value: Single 5 V supply and CMOS/TTL compatibility eliminate level shifters, reducing BOM cost and PCB footprint in space-constrained BCM designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECT | 64 Mbit density, 120 ns access, 3.3 V core with 5 V I/O tolerance - larger capacity but slower and different voltage architecture | Targeted at high-density firmware storage where 64 Kbit is insufficient; requires level translation for pure 5 V systems | Select only if memory expansion beyond 64 Kbit is required and 3.3 V/5 V mixed-supply design is acceptable |
| Microchip 28C64B-25J | Same 64 Kbit organization, 250 ns access, 5 V-only, no page write - slower read, no burst capability, simpler control logic | Suitable for cost-sensitive, low-speed applications where firmware update frequency is minimal and timing margins are generous | Choose when budget constraints outweigh performance needs and page write functionality is unnecessary |
Compared with ST M28W640ECT and Microchip 28C64B-25J, the AT28HC64B-90PU delivers optimal balance of speed (90 ns), efficiency (10 ms page write), and 5 V simplicity - making it the preferred choice for industrial and embedded systems requiring reliable, fast, and easy-to-integrate non-volatile storage.
Availability
AT28HC64B-90PU is available at Aetrix Electronics and suitable for industrial control firmware storage, embedded system parameter backup, and medical device calibration archiving requiring stable component supply across extended product lifecycles.
Supply support for AT28HC64B-90PU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, non-volatile memory, and secure authentication ICs for industrial, automotive, and consumer applications.
The AT28HC64B product line was designed for high-reliability, 5 V parallel EEPROM applications demanding fast access, robust write protection, and long-term data integrity in harsh environments.
FAQ
What is the maximum page write cycle time for AT28HC64B-90PU?
The AT28HC64B-90PU has a maximum page write cycle time of 10 ms under standard conditions. This value is specified in the AC Write Characteristics table and applies to all variants including AT28HC64B-90PU. The optional AT28HC64BF variant achieves 2 ms, but that is not applicable to the AT28HC64B-90PU.
Does AT28HC64B-90PU support both hardware and software write protection?
Yes, AT28HC64B-90PU implements dual-layer write protection: hardware features include VCC sensing (<3.8 V disables writes), 5 ms power-on delay, and noise filtering on WE/CE; software protection uses a three-byte command sequence (AAh/55h/A0h) to enable/disable write lock, shipped disabled from factory.
What package type is used for AT28HC64B-90PU?
AT28HC64B-90PU is packaged in a 28-lead PDIP (Plastic Dual Inline Package), 0.600" wide, with JEDEC-standard pinout. Pin 1 is located at the top-left corner with a notch or dot marking; pins 1 and 14 are designated NC (No Connect) and must remain unconnected.
Can AT28HC64B-90PU be used in industrial temperature environments?
Yes, AT28HC64B-90PU is rated for industrial temperature operation from −40°C to +85°C. This specification is confirmed in Section 5 "DC and AC Operating Range" of the datasheet and applies specifically to the -90PU suffix variant.
How does write completion detection work on AT28HC64B-90PU?
AT28HC64B-90PU supports two independent write completion detection methods: DATA polling (I/O7 returns complement of last written byte until completion, then true data) and toggle-bit detection (I/O6 toggles between 0 and 1 during write, stops toggling upon completion). Both methods allow host software to avoid fixed timeouts.
AT28HC64B-90PU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-DIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-PDIP
AT28HC64B-90PU FAQ
1.How can I place an order for AT28HC64B-90PU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-90PU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-90PU reliable?
The price and inventory of AT28HC64B-90PU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-90PU is usually 5 days.
3.What payment methods are accepted for AT28HC64B-90PU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-90PU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64B-90PU?
AT28HC64B-90PU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-90PU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-90PU?
For technical support, including AT28HC64B-90PU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-90PU requirements.
6.How does Aetrix verify that AT28HC64B-90PU is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-90PU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-90PU meets industry standards.
7.What is the process for return or replacement of AT28HC64B-90PU?
All AT28HC64B-90PU units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-90PU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-90PU part is unused and in its original packaging.
Return procedure for AT28HC64B-90PU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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