Microchip Technology AT28HC64B-90SC
- Part No.:
- AT28HC64B-90SC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28HC64B-90SC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,682
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Product details
Overview
AT28HC64B-90SC from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 90 ns maximum read access time, 10 ms page write cycle, and hardware/software data protection. It operates from a single 5 V ±10% supply and supports commercial temperature range (0°C to 70°C) in 28-lead SOIC package. Used for nonvolatile configuration storage in industrial controllers and embedded instrumentation.
For engineers reviewing the AT28HC64B-90SC datasheet, AT28HC64B-90SC pinout, AT28HC64B-90SC application, or AT28HC64B-90SC equivalent, key selection criteria include page-write timing (10 ms/2 ms option), DATA polling and toggle-bit write completion detection, CMOS/TTL I/O compatibility, 100 µA standby current, and software data protection enable/disable sequences.
Technical Context
The AT28HC64B-90SC implements a static RAM-compatible interface with dual-line chip enable (CE) and output enable (OE) control to prevent bus contention. Its internal 64-byte page register latches addresses and data during page writes, freeing the address/data bus for concurrent operations.
Write completion is verified via two independent methods: DATA polling on I/O7 (complement-to-data during write, true data after completion) and toggle-bit behavior on I/O6 (toggling during write, stable after completion). Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable nonvolatile storage |
| Read Access Time | 90 ns max - determines minimum CPU wait-state insertion for direct bus interfacing |
| Page Write Cycle | 10 ms max (standard) - enables burst programming of up to 64 bytes without external timing control |
| Standby Current | 100 µA CMOS - supports low-power retention in battery-backed systems |
| Endurance | 100,000 write/erase cycles - specifies field-replaceable lifetime under frequent reconfiguration |
| Data Retention | 10 years at 25°C - guarantees long-term validity of stored calibration or setup parameters |
| Supply Voltage | 5 V ±10% - compatible with legacy 5 V logic rails without level-shifting |
Pinout & Package
AT28HC64B-90SC is packaged in a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC), compliant with JEDEC MS-013 and RoHS/Green (Pb/Halide-free) requirements.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations (A12 = MSB) |
| I/O0–I/O7 | Bi-directional Data Bus | Byte-wide data path for read/write; high-impedance when CE or OE inactive |
| CE | Chip Enable | Active-low global device select; must be low for any access (read or write) |
| OE | Output Enable | Active-low read strobe; controls output buffer enable independently of CE |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data for byte or page write |
| VCC | Power Supply | +5 V ±10% main supply; powers core logic and I/O buffers |
| GND | Ground | Reference return for all signals and power; requires low-impedance PCB connection |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-wide Pinout | Ensures drop-in compatibility with legacy SRAM/EEPROM sockets and existing PCB layouts |
| 64-byte Page Register | Reduces firmware overhead by enabling sequential multi-byte writes within one internal cycle |
| DATA Polling & Toggle Bit | Eliminates need for fixed write-time delays; allows real-time status monitoring via I/O7 or I/O6 |
| Software Data Protection (SDP) | User-configurable write lock requiring 3-byte command sequence; persists across power cycles |
| Hardware Write Inhibit | VCC sense, 5 ms power-up delay, and 15 ns noise filtering prevent spurious writes during brown-out |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning constants, and alarm thresholds in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during boot and runtime parameter updates via parallel bus. Use Value: 100,000-cycle endurance ensures reliable recalibration over 10+ years of daily maintenance cycles. |
Use Scenario: Retaining sensor offset/gain coefficients and regulatory compliance settings in portable diagnostic equipment. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage for FDA-mandated calibration records with software write protection enabled. Use Value: SDP prevents accidental overwrite during field service while allowing authorized updates via validated command sequences. |
| Automotive Body Control Module | Test Equipment Setup Profiles |
Use Scenario: Holding seat/mirror position presets and lighting configuration in 12 V automotive systems with transient-suppressed 5 V rail. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to microcontroller GPIOs; withstands -40°C to +85°C extended temp variants (JI/SI). Use Value: 10-year data retention meets OEM requirements for vehicle lifetime calibration persistence without backup battery. |
Use Scenario: Saving user-defined test sequences, fixture IDs, and pass/fail thresholds in automated benchtop testers. IC Role / Device Role / Timing Role: High-speed (90 ns) read access minimizes test cycle time during setup loading; page write accelerates profile updates. Use Value: 10 ms page write reduces firmware update latency by >95% versus byte-by-byte programming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECB90N6 | 64 Mbit (8M × 8), 90 ns access, 3.3 V supply only; no software data protection | Requires level-shifting for 5 V systems; suited for higher-density, lower-voltage designs | Select if migrating to 3.3 V architecture and needing greater capacity; not pin-compatible |
| ON Semiconductor CAT28C64B-90SC | Identical 64 Kbit organization, 90 ns speed, SOIC-28 package, and 5 V operation; same JEDEC pinout | Drop-in replacement with identical timing, protection features, and DC specs per datasheet Rev. 1.0 | Valid second-source option with full functional and mechanical equivalence; verify SDP command compatibility |
Compared with AT28HC64B-90SC, the CAT28C64B-90SC offers identical pinout, timing, and feature set as a qualified second source, while the ST M28W640ECB90N6 provides higher density at 3.3 V but requires board-level voltage and interface redesign.
Availability
AT28HC64B-90SC is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, and automotive body electronics requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for AT28HC64B-90SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains its parallel EEPROM portfolio for legacy system support and industrial reliability requirements.
The AT28HC64B-90SC belongs to Atmel's high-reliability parallel EEPROM family, designed for applications demanding proven nonvolatile storage with deterministic write timing and robust data integrity in harsh environments.
FAQ
What is the maximum page write cycle time for AT28HC64B-90SC?
The AT28HC64B-90SC has a standard maximum page write cycle time of 10 ms. An optional 2 ms version is available through special ordering (contact Microchip Sales); the -90SC suffix denotes the 10 ms variant. This timing is internally controlled and does not require external clocking or polling during execution.
Does AT28HC64B-90SC support both hardware and software write protection?
Yes, AT28HC64B-90SC implements dual-layer protection: hardware features include VCC sensing (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs; software data protection (SDP) is enabled/disabled via documented 3-byte command sequences written to specific addresses, and remains active across power cycles.
How is write completion detected on AT28HC64B-90SC?
AT28HC64B-90SC provides two independent methods: DATA polling reads I/O7 - it outputs the complement of the last written byte during write, then true data upon completion; toggle bit monitors I/O6 - it toggles between 0 and 1 during write, then stabilizes to valid data once complete. Both can be polled at any time during the cycle.
What package type is used for AT28HC64B-90SC?
AT28HC64B-90SC uses a 28-lead plastic gull-wing small outline integrated circuit (SOIC) package, 0.300" wide, with JEDEC MS-013 compliance and green (Pb/Halide-free) construction. Pin 1 is marked by a notch or dot; dimensions are 17.7–18.1 mm length × 7.4–7.6 mm width × 2.35–2.65 mm height.
Is AT28HC64B-90SC compatible with standard SRAM interfaces?
Yes, AT28HC64B-90SC is accessed like a static RAM: CE and OE low with WE high enables read mode; CE and WE low with OE high initiates write. Its JEDEC-approved byte-wide pinout and CMOS/TTL-compatible I/O allow direct substitution in many SRAM-based designs without logic changes, though write timing differs.
AT28HC64B-90SC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28HC64B-90SC FAQ
1.How can I place an order for AT28HC64B-90SC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-90SC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-90SC reliable?
The price and inventory of AT28HC64B-90SC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-90SC is usually 5 days.
3.What payment methods are accepted for AT28HC64B-90SC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-90SC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64B-90SC?
AT28HC64B-90SC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-90SC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-90SC?
For technical support, including AT28HC64B-90SC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-90SC requirements.
6.How does Aetrix verify that AT28HC64B-90SC is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-90SC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-90SC meets industry standards.
7.What is the process for return or replacement of AT28HC64B-90SC?
All AT28HC64B-90SC units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-90SC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-90SC part is unused and in its original packaging.
Return procedure for AT28HC64B-90SC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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