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Microchip Technology AT28HC64B-90SU-T
- Part No.:
- AT28HC64B-90SU-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28HC64B-90SU-T.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,236
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Product details
Overview
AT28HC64B-90SU-T from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 90 ns read access time, hardware/software data protection, and page write capability supporting up to 64-byte writes in ≤10 ms. It operates from a single 5 V ±10% supply and targets firmware storage, configuration memory, and calibration data retention in industrial control systems.
For engineers reviewing the AT28HC64B-90SU-T datasheet, AT28HC64B-90SU-T pinout, AT28HC64B-90SU-T application, or AT28HC64B-90SU-T equivalent, key selection criteria include verified 90 ns read timing, CMOS/TTL-compatible I/O, industrial temperature range (−40°C to +85°C), page write endurance (100,000 cycles), and software data protection enable/disable command sequence compatibility.
Technical Context
The AT28HC64B-90SU-T implements a static RAM–like interface with dual-line chip enable (CE) and output enable (OE) control to prevent bus contention. Its internal 64-byte page register latches address and data during page write operations, freeing the bus for concurrent system activity.
Write completion detection uses either DATA polling (I/O7 complement toggle) or Toggle Bit (I/O6 toggling), both functional during any phase of the write cycle. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable nonvolatile storage |
| Read Access Time | 90 ns maximum - ensures compatibility with 11 MHz bus timing in legacy microcontroller systems |
| Page Write Cycle | 10 ms maximum - enables burst programming of up to 64 bytes without external timing control |
| Endurance | 100,000 write/erase cycles - supports field-updatable firmware with multi-year service life |
| Data Retention | 10 years at 85°C - guarantees calibration or configuration data integrity in harsh industrial environments |
| Supply Voltage | 5 V ±10% - interoperable with standard TTL/CMOS logic rails without level-shifting |
| Standby Current | 100 µA CMOS - minimizes quiescent power in always-on embedded controllers |
Pinout & Package
AT28HC64B-90SU-T is packaged in a 28-lead SOIC (Small Outline Integrated Circuit), 0.300" wide body, JEDEC MS-013 compliant, with lead pitch of 1.27 mm and RoHS-compliant green (Pb/halide-free) finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 byte locations; A6–A12 define page boundaries for page write |
| I/O0–I/O7 | Bidirectional Data Bus | CMOS/TTL-compatible 8-bit data path for read/write; supports DATA polling (I/O7) and Toggle Bit (I/O6) |
| CE | Chip Enable | Active-low device select; must be low with OE low and WE high for read; used with WE for write initiation |
| OE | Output Enable | Active-low output gate; controls tri-state buffer; high during write to avoid bus conflict |
| WE | Write Enable | Active-low write strobe; falling edge latches address; rising edge latches data in byte/page mode |
| VCC | Power Supply | +5 V ±10% main supply; powers core logic and I/O buffers |
| GND | Ground Reference | Signal and power return; decoupling capacitor required near VCC pin |
| NC | No Connect | Unbonded pins (positions 1 and 14 in SOIC top view); must remain unconnected per datasheet |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-wide Pinout | Direct drop-in replacement for industry-standard 28-pin parallel EEPROMs and SRAMs without PCB redesign |
| Software Data Protection (SDP) | User-configurable write lock via 3-byte command sequence (AAh/55h/A0h) to prevent accidental firmware corruption |
| Hardware Write Inhibit | VCC sense, 5 ms power-on delay, and 15 ns noise filtering eliminate spurious writes during power transients |
| 64-byte Page Register | Enables efficient bulk programming - reduces host CPU overhead by >90% vs. byte-by-byte writes |
| Device Identification Area | 64 extra bytes (1FC0h–1FFFh) accessible via 12 V on A9 for unique serialization or calibration traceability |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Memory |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during boot and runtime via parallel bus; 90 ns read latency meets real-time scan cycle deadlines. Use Value: Ensures deterministic startup behavior and eliminates need for battery-backed SRAM, reducing BOM cost and maintenance. | Use Scenario: Retaining sensor calibration coefficients and usage logs in portable diagnostic equipment operating across −20°C to +60°C ambient. IC Role / Device Role / Timing Role: High-reliability data retention element; 10-year data retention at 85°C exceeds medical device shelf-life requirements. Use Value: Eliminates recalibration drift over time and supports regulatory audit trails without external EEPROM management ICs. |
| Automotive Body Control Module (BCM) | Test Equipment Firmware Storage |
Use Scenario: Holding seat position presets, mirror settings, and lighting profiles in automotive BCMs subjected to thermal cycling and EMI. IC Role / Device Role / Timing Role: Robust parameter storage with hardware write protection active during ignition transients; operates across −40°C to +85°C. Use Value: Prevents memory corruption during load dump or cold crank events, improving ASIL-B compliance readiness. | Use Scenario: Storing FPGA bitstreams, instrument calibration constants, and self-test routines in benchtop test equipment requiring field updates. IC Role / Device Role / Timing Role: Field-programmable firmware repository; page write enables fast reprogramming without interrupting production test flow. Use Value: Reduces firmware update time from minutes to seconds, increasing test throughput and minimizing downtime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28HC64B-90JU | Same die, 32-lead PLCC package; larger footprint, different thermal mass and board area | Suitable for through-hole or socketed prototyping; less suitable for high-density SMT production | Select when mechanical mounting or socket compatibility is prioritized over board space |
| AT28HC64B-90TU | Same die, 28-lead TSOP package; thinner profile (1.20 mm max height), tighter pitch (0.55 mm) | Better suited for space-constrained handheld or portable designs; requires finer-pitch PCB layout | Select when Z-height or PCB area is constrained and reflow process supports TSOP |
Compared with AT28HC64B-90JU and AT28HC64B-90TU, the AT28HC64B-90SU-T offers optimal balance of manufacturability, thermal performance, and legacy board compatibility in 28-pin SOIC form factor - ideal for industrial upgrades and volume production where assembly yield and long-term supply stability are critical.
Availability
AT28HC64B-90SU-T is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, automotive body electronics, and test equipment requiring stable component supply and long-term lifecycle support.
Supply support for AT28HC64B-90SU-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and manufacturing continuity for the AT28HC64B family.
The AT28HC64B series was designed as a high-reliability, pin-compatible upgrade path from older EPROM and early EEPROM technologies, targeting legacy parallel-bus systems needing robust, low-power nonvolatile storage.
FAQ
What is the maximum page write size supported by the AT28HC64B-90SU-T?
The AT28HC64B-90SU-T supports page write operations of 1 to 64 bytes within a single internal programming cycle. All bytes must reside on the same page, defined by address bits A6–A12. The 64-byte page register allows the host to load data sequentially within 150 µs intervals, enabling efficient bulk programming without external timing circuitry. This capability is confirmed in the AC Write Characteristics table and Page Mode Write Waveforms section of the official datasheet.
Does the AT28HC64B-90SU-T require a 12 V supply for normal operation?
No, the AT28HC64B-90SU-T operates from a single 5 V ±10% supply during standard read and write operations. A 12 V ±0.5 V supply on pin A9 is required only for accessing the 64-byte device identification area (addresses 1FC0h–1FFFh); it is not needed for main memory reads, writes, or page operations. This voltage is strictly isolated to the ID region and does not affect core functionality.
How does software data protection (SDP) work on the AT28HC64B-90SU-T?
Software data protection on the AT28HC64B-90SU-T is enabled by writing three specific bytes (AAh, 55h, A0h) to designated addresses (1555h, 0AAAh, 1555h). Once activated, all subsequent writes require repeating this sequence before data - ensuring accidental overwrites are blocked. SDP remains active across power cycles and can be disabled using a separate 5-byte command (AAh, 55h, 80h, AAh, 20h). This mechanism is fully documented in the Software Data Protection Algorithm diagrams.
Can the AT28HC64B-90SU-T be used as a direct replacement for SRAM in existing designs?
Yes - the AT28HC64B-90SU-T uses a static RAM–like interface: CE and OE control read access, while WE initiates writes. It requires no external timing components and supports identical address/data bus timing during reads. However, write cycles take up to 10 ms, so host firmware must implement DATA polling or Toggle Bit detection to avoid bus conflicts - unlike true SRAM, which supports simultaneous read/write.
What is the meaning of the "-SU" suffix in AT28HC64B-90SU-T?
The "-SU" suffix in AT28HC64B-90SU-T denotes the 28-lead SOIC (Small Outline IC) package per Atmel's ordering nomenclature. The final "-T" indicates tape-and-reel packaging for automated SMT assembly. This matches the "28S" package code in the Ordering Information table and confirms the device uses the JEDEC MS-013 compliant SOIC footprint with 1.27 mm lead pitch and green (Pb/halide-free) finish.
AT28HC64B-90SU-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28HC64B-90SU-T FAQ
1.How can I place an order for AT28HC64B-90SU-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-90SU-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-90SU-T reliable?
The price and inventory of AT28HC64B-90SU-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-90SU-T is usually 5 days.
3.What payment methods are accepted for AT28HC64B-90SU-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-90SU-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64B-90SU-T?
AT28HC64B-90SU-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-90SU-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-90SU-T?
For technical support, including AT28HC64B-90SU-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-90SU-T requirements.
6.How does Aetrix verify that AT28HC64B-90SU-T is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-90SU-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-90SU-T meets industry standards.
7.What is the process for return or replacement of AT28HC64B-90SU-T?
All AT28HC64B-90SU-T units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-90SU-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-90SU-T part is unused and in its original packaging.
Return procedure for AT28HC64B-90SU-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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