Microchip Technology AT28HC64B-90TC
- Part No.:
- AT28HC64B-90TC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-TSSOP (0.465", 11.80mm Width)
- Datasheet:
-
AT28HC64B-90TC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28TSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28HC64B-90TC from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 90 ns read access time, 10 ms page write cycle (standard), and CMOS/TTL-compatible I/O. It operates on single 5 V ±10% supply and supports hardware/software data protection for embedded nonvolatile storage in industrial control modules.
For engineers reviewing the AT28HC64B-90TC datasheet, AT28HC64B-90TC pinout, AT28HC64B-90TC application, or AT28HC64B-90TC equivalent, key selection considerations include its 90 ns access timing, 64-byte page write capability, 100 µA standby current, DATA polling/toggle bit write completion detection, and industrial temperature range support (-40°C to +85°C).
Technical Context
The AT28HC64B-90TC implements a parallel interface with CE/OE/WE control logic enabling SRAM-like read/write operation without external timing components. Its internal 64-byte page register latches address and data during page writes, freeing the bus for concurrent operations.
Write completion is verified via dual methods: DATA polling (I/O7 complement toggle) and Toggle Bit (I/O6 toggling), both usable at any point during tWC. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits); sufficient for firmware patch storage or configuration parameter tables in microcontroller systems. |
| Read Access Time | 90 ns maximum; enables direct interfacing with 10 MHz–12 MHz microcontrollers without wait states. |
| Page Write Cycle | 10 ms max (standard); allows efficient bulk updates of up to 64 bytes per write command, reducing host CPU overhead. |
| Standby Current | 100 µA typical (CMOS mode); critical for low-power battery-backed applications like metering or sensor nodes. |
| Endurance | 100,000 write/erase cycles; supports field-upgradable devices requiring frequent calibration or logging updates. |
| Data Retention | 10 years at 85°C; ensures long-term reliability in industrial environments without refresh circuitry. |
| Supply Voltage | 5 V ±10%; compatible with legacy 5 V logic families and eliminates need for voltage translation. |
Pinout & Package
AT28HC64B-90TC is housed in a 28-lead Thin Small Outline Package (TSOP), 8 mm × 13.4 mm footprint, compliant with JEDEC MO-183. Pin 1 identifier located at top-left corner with 0°–5° lead angle.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte writes. |
| I/O0–I/O7 | Bidirectional Data Bus | Byte-wide parallel interface; supports true read-modify-write without external latches. |
| CE | Chip Enable | Active-low chip select; when high, device enters high-impedance standby, reducing system bus loading. |
| OE | Output Enable | Active-low output control; used with CE to prevent bus contention during multi-device sharing. |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; initiates byte or page programming sequence. |
| VCC / GND | Power Supply | Single 5 V supply with decoupling required within 1 cm; ground plane essential for stable 90 ns timing margins. |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-wide Pinout | Direct drop-in replacement for industry-standard 28-pin parallel EEPROMs and EPROMs in existing PCB layouts. |
| 64-byte Page Write | Reduces write latency by 98% vs. sequential byte writes-64 bytes programmed in one 10 ms cycle instead of 64 × 10 ms. |
| Hardware + Software Data Protection | VCC sensing, 5 ms power-on delay, and user-configurable software lock prevent accidental writes during brown-out or reset. |
| DATA Polling & Toggle Bit | Eliminates need for fixed delay timers; host reads I/O7 or monitors I/O6 to detect write completion with zero timing uncertainty. |
| Industrial Temperature Range | Rated for -40°C to +85°C case temperature; validated for use in motor drives, PLC I/O modules, and outdoor telecom equipment. |
Applications
| Industrial PLC Configuration Storage | Embedded System Firmware Patching |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during boot and runtime; 90 ns read speed ensures real-time parameter lookup without scan cycle penalty. Use Value: 100,000 endurance cycles support weekly firmware updates over 5+ years; software protection prevents corruption during power loss during parameter upload. | Use Scenario: Holding field-upgradable bootloader patches and safety-critical firmware hotfixes in medical infusion pumps and diagnostic imaging subsystems. IC Role / Device Role / Timing Role: Secondary code storage accessed only during update sequences; page write enables full 64-byte patch commit in <10 ms, minimizing system downtime. Use Value: 10-year data retention guarantees patch integrity across product lifecycle; 100 µA standby current avoids draining backup batteries during idle periods. |
| Smart Meter Calibration Data | Automotive Body Control Module Settings |
Use Scenario: Recording meter-specific calibration coefficients, tariff schedules, and tamper-event logs in ANSI C12.22-compliant electricity meters. IC Role / Device Role / Timing Role: Secure parameter vault with hardware write inhibit; A9 high-voltage access enables dedicated 64-byte ID sector for metrology certification traceability. Use Value: Dual protection (VCC sense + software lock) prevents unauthorized calibration changes; industrial temp rating ensures accuracy across outdoor mounting conditions. | Use Scenario: Storing seat position presets, mirror angles, and lighting profiles in automotive body control units (BCUs) with CAN/LIN interfaces. IC Role / Device Role / Timing Role: Local configuration store accessed by 8-bit MCU during power-up; 5 V compatibility eliminates level-shifting for legacy BCU designs. Use Value: JEDEC pinout allows reuse of existing PCB footprints from prior EEPROM generations; green (Pb/Halide-free) TSOP package meets automotive RoHS requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-90JC | Same 64K × 8 architecture and 90 ns timing, but in 32-lead PLCC package with different pinout (32 pins vs. 28) and no TSOP option. | Requires PCB redesign due to 32-pin PLCC footprint and relocated I/O/CE/OE/WE pins; not suitable for space-constrained TSOP layouts. | Select only if PLCC socketing is required for prototyping or legacy board reuse. |
| ST M28W640ECB90N6 | 64 Mbit (8M × 8) density, 90 ns access, but requires 3.3 V supply and has different write enable protocol (no DATA polling on I/O7). | Not pin-compatible; incompatible voltage domain necessitates level shifters; lacks hardware VCC-sense protection. | Consider only for new 3.3 V designs where higher density justifies revalidation effort and added BOM cost. |
Compared with AT28HC64B-90TC, AT28C64B-90JC demands mechanical redesign while ST M28W640ECB90N6 introduces voltage and protocol incompatibility-neither offers drop-in replacement capability, making AT28HC64B-90TC the optimal choice for 5 V, TSOP-based industrial upgrades.
Availability
AT28HC64B-90TC is available at Aetrix Electronics and suitable for industrial control systems, smart metering infrastructure, and automotive body electronics requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for AT28HC64B-90TC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for the legacy AT28HC series. The company specializes in scalable microcontrollers, analog, and nonvolatile memory solutions for industrial and automotive markets.
The AT28HC64B product line was designed specifically for reliable, low-power, parallel-interface EEPROM replacement in 5 V embedded systems where SRAM-like simplicity and robust data retention are mandatory.
FAQ
What is the maximum page write size supported by the AT28HC64B-90TC?
The AT28HC64B-90TC supports a maximum page write size of 64 bytes. This is enabled by its internal 64-byte page register, which latches address and data during a single write command. All bytes written in one page operation must reside on the same page, defined by address bits A6–A12. The AT28HC64B-90TC does not support larger page sizes or sector-based erases.
Does the AT28HC64B-90TC require external high-voltage circuitry for normal operation?
No, the AT28HC64B-90TC operates entirely from a single 5 V ±10% supply under standard read/write conditions. High voltage (12 V ±0.5 V on A9) is required only for accessing the optional 64-byte device identification sector (addresses 1FC0H–1FFFH)-not for main array reads, writes, or erases. The AT28HC64B-90TC integrates all necessary charge pumps internally.
How does software data protection work on the AT28HC64B-90TC?
Software data protection (SDP) on the AT28HC64B-90TC is enabled by writing a specific three-byte sequence (0xAA → 0x55 → 0xA0) to addresses 0x5555, 0x2AAA, and 0x5555 respectively. Once activated, all subsequent writes require repeating this sequence before data. The AT28HC64B-90TC ships with SDP disabled, and the feature remains active across power cycles until explicitly disabled using the 0xAA/0x55/0x80/0xAA/0x55/0x20 sequence.
Can the AT28HC64B-90TC be used in place of an EPROM like the 27C64?
No-the AT28HC64B-90TC is an EEPROM with in-system electrical erasure and byte/page write capability, whereas the 27C64 is a UV-erasable EPROM requiring removal and exposure to ultraviolet light. Though both share JEDEC 28-pin DIP/SOIC pinouts, the AT28HC64B-90TC uses WE/CE/OE control logic instead of OE/CE only, and lacks the 27C64's program verify or VPP pin. Direct substitution is electrically and functionally invalid.
What is the purpose of the Toggle Bit (I/O6) on the AT28HC64B-90TC?
The Toggle Bit on I/O6 of the AT28HC64B-90TC provides asynchronous write completion detection: during an active write cycle, successive reads cause I/O6 to toggle between 0 and 1; once the internal programming finishes, I/O6 stabilizes and outputs valid data. This allows host firmware to poll I/O6 without knowledge of tWC duration, eliminating timing margin risks. The AT28HC64B-90TC supports simultaneous use of Toggle Bit and DATA Polling (I/O7) for redundancy.
AT28HC64B-90TC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.465", 11.80mm Width)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSOP
AT28HC64B-90TC FAQ
1.How can I place an order for AT28HC64B-90TC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64B-90TC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64B-90TC reliable?
The price and inventory of AT28HC64B-90TC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64B-90TC is usually 5 days.
3.What payment methods are accepted for AT28HC64B-90TC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64B-90TC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64B-90TC?
AT28HC64B-90TC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64B-90TC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64B-90TC?
For technical support, including AT28HC64B-90TC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64B-90TC requirements.
6.How does Aetrix verify that AT28HC64B-90TC is sourced from the original manufacturer or authorized distributors?
All AT28HC64B-90TC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64B-90TC meets industry standards.
7.What is the process for return or replacement of AT28HC64B-90TC?
All AT28HC64B-90TC units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64B-90TC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64B-90TC part is unused and in its original packaging.
Return procedure for AT28HC64B-90TC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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