Microchip Technology AT28HC64BF-12PU
- Part No.:
- AT28HC64BF-12PU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
AT28HC64BF-12PU.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28DIP
- Quantity:
- Payment:

- Shipping:

Inventory:2,316
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Product details
Overview
AT28HC64BF-12PU from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 120 ns maximum read access time, hardware/software data protection, and page write capability supporting up to 64-byte writes in ≤2 ms. It operates from a single 5 V ±10% supply and targets nonvolatile storage in industrial control modules requiring reliable reprogramming without external timing circuitry.
For engineers reviewing the AT28HC64BF-12PU datasheet, AT28HC64BF-12PU pinout, AT28HC64BF-12PU application, or AT28HC64BF-12PU equivalent, key selection criteria include its 100,000-cycle endurance, 10-year data retention, CMOS/TTL-compatible I/O, industrial temperature range (–40°C to +85°C), and support for DATA polling and toggle-bit write completion detection.
Technical Context
The AT28HC64BF-12PU implements a static RAM-like interface with dual-line chip enable (CE) and output enable (OE) control to prevent bus contention. Its internal 64-byte page register latches address and data during page write operations, freeing the bus for concurrent system activity.
Write cycles are self-timed using an internal control timer; completion is signaled via DATA polling on I/O7 or toggle-bit behavior on I/O6. Hardware protection includes VCC sense (<3.8 V inhibits writes), 5 ms power-on delay, and noise filtering on CE/WE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 words × 8 bits); supports byte- and page-level nonvolatile storage without external erase circuitry. |
| Read Access Time | 120 ns max; enables direct replacement of SRAM in legacy systems where timing margins accommodate this latency. |
| Page Write Cycle | ≤2 ms; allows burst programming of up to 64 bytes within one internal operation, reducing host CPU overhead. |
| Endurance | 100,000 write/erase cycles; ensures long-term reliability in firmware update or configuration logging applications. |
| Data Retention | 10 years at +85°C; guarantees persistent storage integrity across product lifecycles in industrial environments. |
| Supply Voltage | 5 V ±10%; compatible with standard TTL/CMOS logic rails and eliminates need for auxiliary voltage regulators. |
| Operating Temperature | –40°C to +85°C; qualified for use in uncontrolled industrial enclosures and outdoor equipment housings. |
Pinout & Package
AT28HC64BF-12PU is supplied in a 28-lead PDIP (Plastic Dual Inline Package), 0.600" wide, with JEDEC-standard byte-wide pinout. Pin 1 is marked by a notch or dot; pins 1 and 14 are GND and VCC respectively.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte writes. |
| CE | Chip Enable | Active-low global enable; must be low for read/write access; high state places device in standby (≤100 µA). |
| OE | Output Enable | Active-low output gate; controls data bus drive; used with CE to manage bus contention in multi-device systems. |
| WE | Write Enable | Active-low write strobe; initiates byte or page write; combined with CE for robust write inhibition during power transitions. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; carries data during reads and accepts input during writes; CMOS/TTL compatible. |
| GND | Ground Reference | Pin 14; primary return path for VCC and signal currents; requires low-impedance PCB connection. |
| VCC | Power Supply | Pin 28; supplies core logic and memory array; bypass capacitor (0.1 µF) required adjacent to pin. |
| NC | No Connect | Pins 1, 17, and 27 are unconnected; must remain floating per manufacturer specification. |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Operation | Supports 1–64-byte writes in ≤2 ms using internal latching-reduces host processor intervention and improves system throughput. |
| DATA Polling & Toggle Bit | I/O7 complement and I/O6 toggling provide real-time, software-readable status of write completion without requiring timers or interrupts. |
| Hardware Data Protection | VCC sensing, 5 ms power-on delay, and 15 ns noise filtering on CE/WE prevent spurious writes during brown-out or EMI events. |
| Software Data Protection (SDP) | User-configurable lock/unlock via 3-byte command sequence (AAh/55h/A0h or AAh/55h/80h/AAh/20h); persists through power cycles. |
| Extended Identification Area | 64-byte dedicated EEPROM region (1FC0H–1FFFH) accessible via 12 V on A9 for device serialization or calibration data storage. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Logging |
|---|---|
|
Use Scenario: Storing user-defined I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing byte-addressable, field-upgradable storage with deterministic 120 ns read latency. Use Value: Enables zero-downtime parameter updates via page write; 100,000-cycle endurance supports decades of maintenance cycles. |
Use Scenario: Recording sensor calibration coefficients and usage history in portable diagnostic instruments subject to frequent battery changes. IC Role / Device Role / Timing Role: Reliable data logger with hardware write protection ensuring integrity during unexpected power loss. Use Value: 10-year data retention and SDP prevent corruption of critical calibration data across device lifetime. |
| Telecom Line Card Firmware Backup | Automotive Body Control Module Settings |
|
Use Scenario: Holding boot firmware checksums and configuration flags on carrier-grade line cards operating in NEBS-compliant cabinets. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to microcontroller data bus for fast firmware validation at power-up. Use Value: JEDEC-standard pinout simplifies PCB layout reuse; industrial temperature rating ensures stability under thermal cycling. |
Use Scenario: Storing seat position memory, mirror presets, and lighting profiles in automotive body control units. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed during vehicle startup and runtime via standard 8-bit bus. Use Value: Hardware VCC-sense protection prevents inadvertent writes during ignition transients; green Pb/halide-free packaging meets automotive RoHS requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M48T02-120PC1 | Real-time clock + 2 Kbit NV SRAM; no page write; 120 ns read; 5 V only; integrated lithium backup. | RTC-critical systems needing time-stamped logs; not suitable for pure configuration storage due to smaller capacity and different architecture. | Select when timestamped event logging and battery-backed timekeeping are required alongside minimal nonvolatile storage. |
| Microchip 28C64B-12/P | 64 Kbit parallel EEPROM; 120 ns read; same JEDEC pinout; 100,000 cycles; but lacks software data protection and extended ID area. | Cost-sensitive industrial designs where SDP and device identification are not required; identical footprint and timing. | Choose for drop-in compatibility where Atmel-specific features like SDP or 12 V-programmable ID space are unnecessary. |
Compared with ST M48T02-120PC1, AT28HC64BF-12PU offers 32× more storage and page write efficiency but no RTC function; versus Microchip 28C64B-12/P, it adds robust software/hardware write protection and a dedicated 64-byte ID zone-critical for traceability and secure firmware updates.
Availability
AT28HC64BF-12PU is available at Aetrix Electronics and suitable for industrial PLCs, medical instrumentation, telecom line cards, and automotive body control modules requiring stable component supply over extended production lifecycles.
Supply support for AT28HC64BF-12PU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) specialized in high-reliability nonvolatile memory and microcontroller solutions for industrial and automotive markets before its 2016 acquisition.
The AT28HC64BF product line was engineered for robust, pin-compatible EEPROM replacement in legacy 8-bit systems-emphasizing ease of integration, write safety, and long-term data integrity in harsh environments.
FAQ
What is the maximum page write size supported by the AT28HC64BF-12PU?
The AT28HC64BF-12PU supports page write operations of 1 to 64 bytes within a single internal programming cycle. All bytes must reside on the same page, defined by address bits A6–A12. The device internally latches addresses and data, enabling the host to release the bus after initiating the first byte write-reducing CPU overhead compared to sequential byte writes. This capability is confirmed in Section 4.3 of the official datasheet.
Does the AT28HC64BF-12PU require a 12 V supply for normal operation?
No, the AT28HC64BF-12PU operates from a single 5 V ±10% supply during standard read and write operations. A 12 V ±0.5 V supply on pin A9 is required only for accessing the extended 64-byte device identification area (addresses 1FC0H–1FFFH). This high-voltage mode is strictly isolated to that dedicated region and does not affect regular memory access or timing specifications.
How does hardware write protection work on the AT28HC64BF-12PU?
Hardware protection on the AT28HC64BF-12PU includes four mechanisms: (1) VCC sense disables writes if supply drops below ~3.8 V; (2) a 5 ms internal delay after VCC reaches threshold prevents early writes; (3) write inhibition occurs if OE is low, CE is high, or WE is high; and (4) input noise filtering rejects pulses <15 ns on CE/WE. These features are active at power-up and during brown-out conditions, ensuring data integrity without software intervention.
Can the AT28HC64BF-12PU be used as a direct replacement for SRAM in existing designs?
Yes-the AT28HC64BF-12PU uses a static RAM-compatible interface: CE and OE control read access, while WE initiates writes. Its 120 ns read access time and TTL/CMOS-compatible I/O allow drop-in replacement in many SRAM-based systems, provided timing budgets accommodate write cycle delays and software handles DATA polling or toggle-bit detection for write completion. No external address/data latches or timing generators are needed.
What is the purpose of the extra 64 bytes of EEPROM in the AT28HC64BF-12PU?
The additional 64 bytes (addresses 1FC0H–1FFFH) serve as a dedicated device identification area. Accessed only when A9 is raised to 12 V ±0.5 V, this region stores unique calibration data, serial numbers, or manufacturing traceability information-separate from main memory. It retains data for 10 years and supports the same 100,000-cycle endurance, making it ideal for field-serviceable device tracking without consuming user memory space.
AT28HC64BF-12PU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-DIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-PDIP
AT28HC64BF-12PU FAQ
1.How can I place an order for AT28HC64BF-12PU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64BF-12PU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64BF-12PU reliable?
The price and inventory of AT28HC64BF-12PU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64BF-12PU is usually 5 days.
3.What payment methods are accepted for AT28HC64BF-12PU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64BF-12PU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64BF-12PU?
AT28HC64BF-12PU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64BF-12PU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64BF-12PU?
For technical support, including AT28HC64BF-12PU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64BF-12PU requirements.
6.How does Aetrix verify that AT28HC64BF-12PU is sourced from the original manufacturer or authorized distributors?
All AT28HC64BF-12PU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64BF-12PU meets industry standards.
7.What is the process for return or replacement of AT28HC64BF-12PU?
All AT28HC64BF-12PU units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64BF-12PU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64BF-12PU part is unused and in its original packaging.
Return procedure for AT28HC64BF-12PU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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