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Microchip Technology AT28HC64BF-12TU
- Part No.:
- AT28HC64BF-12TU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-TSSOP (0.465", 11.80mm Width)
- Datasheet:
-
AT28HC64BF-12TU.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28TSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,182
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Product details
Overview
AT28HC64BF-12TU from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 120 ns maximum read access time, 2 ms max page write cycle, and industrial temperature range (–40°C to +85°C). It supports hardware/software data protection, DATA polling, and toggle-bit write completion detection for embedded control, firmware storage, and configuration memory in programmable logic controllers and industrial HMIs.
For engineers reviewing the AT28HC64BF-12TU datasheet, AT28HC64BF-12TU pinout, AT28HC64BF-12TU application, or AT28HC64BF-12TU equivalent, this page delivers verified electrical specs, package mapping, real-world use cases, and validated alternative parts - all grounded in the official Microchip AT28HC64BF datasheet (3648A–PEEPR–10/06).
Technical Context
The AT28HC64BF-12TU operates as a drop-in SRAM-compatible nonvolatile memory: reads require CE and OE low with WE high; writes initiate on WE or CE low pulse while OE is high. Its internal 64-byte page register enables simultaneous latching of up to 64 bytes, freeing the bus during internal programming.
Write completion is confirmed via dual methods: DATA polling (I/O7 complement toggles until completion) and toggle-bit detection (I/O6 toggles during write, stabilizes afterward). Hardware protection includes VCC sense (<3.8 V inhibits write), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits) - sufficient for boot code, calibration tables, or device configuration in space-constrained industrial controllers. |
| Read Access Time | 120 ns max - meets timing requirements for 8-bit microcontrollers running at ≤8 MHz with wait-state-free operation. |
| Page Write Cycle | 2 ms max - enables efficient bulk updates (e.g., logging 64 sensor samples) without CPU blocking longer than 2 ms. |
| VCC Supply | 5 V ±10% - compatible with legacy 5 V logic systems without level-shifting circuitry. |
| Standby Current | 100 µA CMOS - supports low-power modes in battery-backed or energy-harvested edge devices. |
| Data Retention | 10 years - ensures long-term reliability for field-deployed equipment with infrequent reprogramming. |
| Endurance | 100,000 write cycles - suitable for applications requiring daily firmware patching over a 27-year service life. |
Pinout & Package
AT28HC64BF-12TU is supplied in a 28-lead Plastic Thin Small Outline Package (TSOP), Type I (8 × 13.4 mm), JEDEC MO-183 compliant, with lead coplanarity ≤0.10 mm and green (Pb/halide-free) finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus (0–8191) selecting one of 8K bytes; A6–A12 define page boundaries for 64-byte page writes. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit detection during write cycles. |
| CE | Chip Enable | Active-low chip select; must be low for read/write; high forces outputs to high-Z and inhibits writes. |
| OE | Output Enable | Active-low output control; low enables data output during read; high disables outputs (high-Z). |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; used with CE for byte or page write initiation. |
| GND / VCC | Power Terminals | Ground reference and 5 V supply; decoupling capacitor required within 1 cm of VCC pin per datasheet layout guidance. |
| NC | No Connect | Unbonded pins (e.g., Pin 1, Pin 14 in TSOP top view); must remain unconnected per JEDEC pinout compliance. |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Operation | Writes 1–64 bytes in ≤2 ms using internal latched address/data - reduces host CPU overhead vs. 64 individual byte writes. |
| DATA Polling & Toggle Bit | Dual, software-transparent write completion detection - eliminates need for fixed delays or external timers in firmware. |
| Software Data Protection (SDP) | User-enabled 3-byte command sequence (AAh/55h/A0h) prevents accidental writes - critical for field-upgradable firmware integrity. |
| Hardware Write Inhibit | VCC sense, 5 ms power-on delay, and 15 ns noise filtering prevent spurious writes during brown-out or EMI events. |
| Extended Identification Area | 64 extra bytes (1FC0H–1FFFH) accessible via 12 V on A9 - enables unique device serialization or calibration data storage. |
Applications
| Industrial PLC Configuration Storage | Firmware Bootloader Memory |
|---|---|
|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed at power-up and runtime; requires 120 ns read access to avoid CPU wait states. Use Value: Enables field reconfiguration without hardware change; 100,000 endurance supports weekly parameter updates over 27+ years. |
Use Scenario: Holding bootloader code and secure boot keys in microcontroller-based edge gateways performing OTA firmware validation. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage for immutable boot logic; SDP prevents overwrite during failed update attempts. Use Value: Prevents bricking during power loss mid-update; 10-year data retention ensures key persistence across product lifecycle. |
| Medical Device Calibration Data | Automated Test Equipment (ATE) Setup Tables |
|
Use Scenario: Retaining sensor calibration coefficients and safety-critical offset values in portable diagnostic instruments. IC Role / Device Role / Timing Role: High-reliability data vault; uses 12 V A9 access to write protected calibration data post-manufacturing. Use Value: Meets IEC 62304 traceability requirements; 100 µA standby current extends battery life in handheld units. |
Use Scenario: Storing test pattern sequences and fixture-specific compensation values in benchtop ATE systems. IC Role / Device Role / Timing Role: Fast-access lookup table memory; 2 ms page writes enable batch loading of 64 test vectors without interrupting test flow. Use Value: Reduces test setup time by 98% vs. byte-by-byte writes; JEDEC pinout ensures compatibility with legacy ATE controller boards. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M48T02-12MH6 | Real-time clock + 2 Kbit NV SRAM; no page write; 10 µA standby; 10-year retention. | RTC-integrated solution for time-stamped logging; lacks 64-byte page write efficiency. | Choose when timestamping and low-power sleep mode outweigh bulk write speed. |
| ON Semiconductor CAT28C64B-12L | Same 64K × 8 architecture, 120 ns access, 2 ms page write; 28-pin SOIC only (no TSOP). | Drop-in replacement for PCBs using SOIC footprint; not mechanically compatible with AT28HC64BF-12TU's TSOP-28. | Choose for SOIC-based designs needing identical electrical behavior and sourcing continuity. |
Compared with ST M48T02-12MH6, AT28HC64BF-12TU provides 32× more memory and faster page writes but lacks RTC; versus CAT28C64B-12L, it shares core functionality but differs in package - making AT28HC64BF-12TU optimal for space-constrained TSOP layouts requiring high-density configuration storage.
Availability
AT28HC64BF-12TU is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, and automated test systems requiring stable component supply, long-lifecycle support, and green packaging compliance.
Supply support for AT28HC64BF-12TU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full technical and manufacturing continuity for the AT28HC64BF family. The company specializes in scalable microcontrollers, analog, and memory solutions for industrial and automotive markets.
The AT28HC64BF series was designed specifically for robust, SRAM-compatible nonvolatile storage in harsh environments - emphasizing write endurance, data retention, and hardware/software write protection for mission-critical firmware and configuration data.
FAQ
What is the maximum operating temperature range for the AT28HC64BF-12TU?
The AT28HC64BF-12TU is rated for industrial temperature operation from –40°C to +85°C. This range is validated per the datasheet's DC and AC operating specifications and applies to all package variants including the TSOP-28. Thermal derating is not required within this envelope, and the device maintains full 120 ns read access and 2 ms page write performance across the full span.
Does the AT28HC64BF-12TU support true 5 V TTL-compatible signaling?
Yes, the AT28HC64BF-12TU features CMOS and TTL-compatible inputs and outputs. Its VIH threshold is 2.0 V minimum and VIL is 0.8 V maximum, meeting standard TTL logic levels. VOH is ≥2.4 V at –400 µA, and VOL is ≤0.4 V at 2.1 mA - ensuring reliable interfacing with legacy 5 V microcontrollers and FPGAs without level shifters.
How does software data protection (SDP) work on the AT28HC64BF-12TU?
SDP on the AT28HC64BF-12TU is enabled by writing three specific bytes (AAh to 1555h, 55h to 0AAAh, A0h to 1555h) in sequence. Once activated, all subsequent writes require repeating this sequence before data. The AT28HC64BF-12TU ships with SDP disabled, and the feature remains active through power cycles until explicitly disabled using the defined 5-byte disable command.
Can the AT28HC64BF-12TU perform page writes across address boundaries?
No. Page writes on the AT28HC64BF-12TU are restricted to a single 64-byte page defined by address bits A6–A12. If a write sequence crosses a page boundary (e.g., from address 0x003F to 0x0040), the device terminates loading after the first 64-byte limit and initiates internal programming. To write across pages, separate page write commands must be issued for each page.
What package type is used for the AT28HC64BF-12TU?
The AT28HC64BF-12TU uses a 28-lead Plastic Thin Small Outline Package (TSOP), Type I, measuring 8 × 13.4 mm. It conforms to JEDEC MO-183, features gull-wing leads, and is Pb/halide-free. Pin 1 is marked by a notch or dot; the pinout matches JEDEC-standard byte-wide parallel EEPROM configurations.
AT28HC64BF-12TU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.465", 11.80mm Width)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSOP
AT28HC64BF-12TU FAQ
1.How can I place an order for AT28HC64BF-12TU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64BF-12TU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64BF-12TU reliable?
The price and inventory of AT28HC64BF-12TU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64BF-12TU is usually 5 days.
3.What payment methods are accepted for AT28HC64BF-12TU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64BF-12TU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64BF-12TU?
AT28HC64BF-12TU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64BF-12TU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64BF-12TU?
For technical support, including AT28HC64BF-12TU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64BF-12TU requirements.
6.How does Aetrix verify that AT28HC64BF-12TU is sourced from the original manufacturer or authorized distributors?
All AT28HC64BF-12TU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64BF-12TU meets industry standards.
7.What is the process for return or replacement of AT28HC64BF-12TU?
All AT28HC64BF-12TU units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64BF-12TU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64BF-12TU part is unused and in its original packaging.
Return procedure for AT28HC64BF-12TU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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