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Microchip Technology AT28HC64BF-70PU
- Part No.:
- AT28HC64BF-70PU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
AT28HC64BF-70PU.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28DIP
- Quantity:
- Payment:
- Shipping:
Inventory:1,671
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Product details
Overview
AT28HC64BF-70PU from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 70 ns read access time, and hardware/software data protection. It supports page write (1–64 bytes), DATA polling and toggle-bit write completion detection, and operates on single 5 V ±10% supply in industrial temperature range (−40°C to +85°C). Used in embedded system configuration storage, firmware parameter retention, and boot code backup.
For engineers reviewing the AT28HC64BF-70PU datasheet, AT28HC64BF-70PU pinout, AT28HC64BF-70PU application, or AT28HC64BF-70PU equivalent, key selection considerations include page-write timing (2 ms max), CMOS standby current (100 µA), endurance (100,000 cycles), data retention (10 years), and software data protection enable/disable sequence compatibility.
Technical Context
The AT28HC64BF-70PU implements a static RAM-compatible interface with dual-line chip enable (CE) and output enable (OE) control for bus contention avoidance. Its internal 64-byte page register latches addresses and data during write cycles, freeing the address/data bus for concurrent operations.
Write completion is verified via I/O7 DATA polling (complement-to-data behavior) or I/O6 toggle-bit detection. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs; software protection uses a three-byte command sequence at addresses 1555H/0AAAH/1555H.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable nonvolatile storage |
| Read Access Time | 70 ns - enables direct replacement of SRAM in legacy 8-bit microcontroller systems without wait-state insertion |
| Page Write Cycle | 2 ms maximum - allows burst programming of up to 64 bytes per cycle, reducing firmware update latency |
| Endurance | 100,000 write/erase cycles - supports field-upgradable device configuration over multi-year product lifecycle |
| Data Retention | 10 years at 85°C - ensures long-term reliability in industrial control and automotive under-hood applications |
| Supply Voltage | 5 V ±10% - compatible with standard TTL/CMOS logic rails and legacy 5 V system designs |
| Standby Current | 100 µA (CMOS mode) - minimizes power draw in battery-backed or low-power sleep states |
Pinout & Package
AT28HC64BF-70PU is packaged in a 28-lead plastic dual in-line package (PDIP), 0.600" wide, with JEDEC-standard byte-wide pinout and no-connect (NC) pins at positions 1 and 14. Pin functions are electrically and mechanically defined per JEDEC MS-011 AB.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface supporting read, byte write, and page write; I/O7 used for DATA polling, I/O6 for toggle-bit detection |
| CE | Chip Enable | Active-low global enable; must be low with OE low for read, or low with WE low for write; high disables outputs and inhibits writes |
| OE | Output Enable | Active-low read control; high-impedance output when high, enabling shared bus operation without external tri-state logic |
| WE | Write Enable | Active-low write strobe; falling edge latches address and data; combined with CE for robust write initiation and noise immunity |
| VCC | Power Supply | +5 V ±10% main supply; powers core logic and I/O buffers; VCC sense circuitry prevents writes below 3.8 V |
| GND | Ground Reference | Signal and power return path; decoupling capacitor required between VCC and GND per layout guidelines |
| NC | No Connect | Pins 1 and 14 are unconnected internally; must remain floating or tied to GND per PCB design rules - not used for signaling or power |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Operation | Enables 1–64 byte writes in ≤2 ms, reducing firmware update time by up to 64× versus byte-by-byte programming |
| DATA Polling & Toggle Bit | Hardware-supported write completion detection on I/O7 and I/O6 eliminates need for fixed delay timers in host firmware |
| Software Data Protection (SDP) | User-configurable write lock via 3-byte command sequence at 1555H/0AAAH/1555H; persists through power cycles |
| Hardware Write Inhibit | VCC sense, 5 ms power-on delay, and 15 ns noise filtering prevent spurious writes during brown-out or EMI events |
| Device Identification Area | 64-byte reserved EEPROM region (1FC0H–1FFFH) accessible via 12 V on A9 for unique device serialization or calibration data |
Applications
| Industrial PLC Configuration Storage | Legacy Embedded System Boot Code Backup |
|---|---|
Use Scenario: Storing user-defined I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers operating continuously in factory environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing deterministic startup state after power loss or reset. Use Value: 100,000-cycle endurance and 10-year data retention ensure parameter integrity across 15+ year equipment lifespans without maintenance. | Use Scenario: Holding boot loader checksums, hardware revision IDs, and factory-calibrated sensor offsets in 8-bit microcontroller-based medical instruments. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to MCU address/data bus, replacing battery-backed SRAM for zero-maintenance operation. Use Value: 70 ns read access matches typical 8 MHz Z80/8051 bus timing, eliminating wait states and preserving real-time response. |
| Point-of-Sale Terminal Firmware Patch Storage | Automotive Body Control Module Parameter Tables |
Use Scenario: Storing hotfix patches and localized language strings in retail terminals updated remotely via secure download protocols. IC Role / Device Role / Timing Role: Secure, page-writable nonvolatile memory supporting field updates without full reflash of main MCU flash. Use Value: Software data protection prevents accidental overwrite during network-initiated updates, while 2 ms page writes minimize downtime during patch application. | Use Scenario: Retaining seat position memory, mirror angle presets, and lighting profiles in automotive BCMs exposed to −40°C to +85°C ambient. IC Role / Device Role / Timing Role: Industrial-grade EEPROM providing reliable parameter storage independent of main ECU power domain. Use Value: CMOS standby current of 100 µA enables always-on storage without draining vehicle battery during extended parking periods. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECT-70N6 | 64 Mbit (8M × 8), 70 ns access, 3.3 V core with 5 V tolerant I/O; no software data protection | Higher density for future-proofing; requires level-shifting in pure 5 V systems; lacks SDP command sequence | Select when migrating to 3.3 V systems or requiring >64 Kbit capacity; verify VCC tolerance and disable SDP-dependent firmware logic |
| ON Semiconductor CAT28C64B-70WI | Identical 64 Kbit/70 ns spec, same PDIP package, but only hardware protection (no software data protection) | Drop-in pinout replacement with identical timing; missing SDP feature limits use in systems requiring dynamic write-lock capability | Select for cost-sensitive 5 V-only designs where software-controlled write lock is unnecessary; confirm absence of SDP does not impact security requirements |
Compared with AT28HC64BF-70PU, M28W640ECT-70N6 offers higher density and lower voltage operation but lacks software data protection and requires I/O voltage translation, while CAT28C64B-70WI provides identical pinout and timing but omits the SDP feature-making AT28HC64BF-70PU the only option supporting both hardware and software write lock in a 5 V, 64 Kbit parallel EEPROM.
Availability
AT28HC64BF-70PU is available at Aetrix Electronics and suitable for industrial PLC configuration storage, legacy embedded system boot code backup, and point-of-sale terminal firmware patch storage requiring stable component supply and long-term obsolescence management.
Supply support for AT28HC64BF-70PU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel parallel EEPROM products including the AT28HC64BF family.
The AT28HC64BF product line was designed for 5 V embedded systems requiring reliable, SRAM-compatible nonvolatile storage with robust write protection-targeting industrial control, instrumentation, and legacy computing platforms.
FAQ
What is the maximum page write size supported by the AT28HC64BF-70PU?
The AT28HC64BF-70PU supports page write operations of 1 to 64 bytes per cycle. All bytes written in a single page cycle must reside within the same 64-byte page boundary, defined by address bits A6–A12. The internal page register latches the entire block, enabling completion in ≤2 ms without host intervention. This capability is confirmed in Section 4.3 and Table 16 of the official datasheet (3648A–PEEPR–10/06).
Does the AT28HC64BF-70PU require a 12 V supply for normal operation?
No, the AT28HC64BF-70PU operates from a single 5 V ±10% supply (VCC) for all standard read, write, and standby functions. A 12 V ±0.5 V supply on pin A9 is required only for accessing the 64-byte device identification area (1FC0H–1FFFH); this is an optional feature and not needed for primary memory operation. All other functionality-including software data protection-uses only 5 V.
How does software data protection work on the AT28HC64BF-70PU?
Software data protection (SDP) on the AT28HC64BF-70PU is enabled by writing three specific bytes (AAH, 55H, A0H) to addresses 1555H, 0AAAH, and 1555H respectively. Once activated, all subsequent writes require repeating this sequence before data. SDP remains active across power cycles and is disabled using a separate five-byte sequence (AAH, 55H, 80H, AAH, 20H). This mechanism is detailed in Sections 4.6.2 and Figures 19–20 of the datasheet.
Can the AT28HC64BF-70PU be used as a direct replacement for SRAM in existing designs?
Yes-the AT28HC64BF-70PU features SRAM-compatible read/write timing and JEDEC-standard byte-wide pinout, allowing drop-in replacement in many 8-bit systems. Its 70 ns read access time matches common fast SRAMs, and CE/OE dual-control prevents bus contention. However, write cycles require explicit polling or toggle-bit checking, unlike SRAM's instantaneous writes; firmware must be modified to handle write completion detection.
What packaging options are available for the AT28HC64BF-70PU?
The AT28HC64BF-70PU specifically denotes the 28-lead plastic dual in-line package (PDIP), 0.600" wide (package code P6). Other speed/package variants exist (e.g., -70JU = PLCC, -70SU = SOIC), but AT28HC64BF-70PU refers exclusively to the PDIP variant. Mechanical dimensions and lead finish comply with JEDEC MS-011 AB and RoHS-compliant green (Pb/halide-free) specifications per Section 30.2 of the datasheet.
AT28HC64BF-70PU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-DIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 70 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-PDIP
AT28HC64BF-70PU FAQ
1.How can I place an order for AT28HC64BF-70PU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28HC64BF-70PU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28HC64BF-70PU reliable?
The price and inventory of AT28HC64BF-70PU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28HC64BF-70PU is usually 5 days.
3.What payment methods are accepted for AT28HC64BF-70PU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28HC64BF-70PU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28HC64BF-70PU?
AT28HC64BF-70PU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28HC64BF-70PU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28HC64BF-70PU?
For technical support, including AT28HC64BF-70PU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28HC64BF-70PU requirements.
6.How does Aetrix verify that AT28HC64BF-70PU is sourced from the original manufacturer or authorized distributors?
All AT28HC64BF-70PU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28HC64BF-70PU meets industry standards.
7.What is the process for return or replacement of AT28HC64BF-70PU?
All AT28HC64BF-70PU units undergo pre-shipment inspection (PSI). If there is an issue with AT28HC64BF-70PU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28HC64BF-70PU part is unused and in its original packaging.
Return procedure for AT28HC64BF-70PU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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