Microchip Technology AT28LV010-20JI
- Part No.:
- AT28LV010-20JI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28LV010-20JI.pdf
- Description:
- IC EEPROM 1MBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28LV010-20JI from Atmel is a 1-Mbit (128K × 8) low-voltage paged parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, and single 3.3V ±10% supply operation. It supports automatic 1–128-byte page writes with internal latching and timer control, and delivers 15 mA active current and 20 µA CMOS standby current for embedded memory applications requiring nonvolatile storage in industrial temperature range (−40°C to +85°C).
For engineers reviewing the AT28LV010-20JI datasheet, AT28LV010-20JI pinout, AT28LV010-20JI application, or AT28LV010-20JI equivalent, key selection criteria include its 200 ns read timing, hardware/software write protection, DATA polling and toggle-bit write completion detection, 100,000K endurance, and PLCC-32 industrial-grade packaging.
Technical Context
The AT28LV010-20JI operates as a drop-in SRAM-compatible nonvolatile memory: CE/OE/WE control logic enables standard read cycles with high-impedance outputs on deselect, while write cycles require a three-byte Software Data Protection (SDP) command sequence before any data programming. Its internal 128-byte page register latches address and data on WE or CE edge transitions, decoupling bus activity during internal programming.
Write completion is verified via I/O7 DATA polling (complement-to-data then true data) or I/O6 toggle-bit behavior-both usable at any point during the ≤10 ms internal write cycle. Hardware protections include VCC power-on delay (~5 ms), noise filtering (<15 ns pulse rejection), and write inhibit via OE low/CE high/WE high states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 1 Mbit (131,072 × 8), enabling full firmware or configuration storage in space-constrained systems |
| Read Access Time | 200 ns max - meets real-time boot and lookup latency requirements in microcontroller-based designs |
| Page Write Cycle Time | 10 ms max - defines minimum interval between successive page writes in firmware update sequences |
| VCC Supply Range | 3.3V ±10% - compatible with modern 3.3V logic domains without level-shifting circuitry |
| Endurance | 100,000K write/erase cycles - supports frequent field-updatable parameter logging over product lifetime |
| Data Retention | 10 years at 85°C - ensures long-term reliability in industrial environments without refresh |
| Operating Temperature | −40°C to +85°C - qualified for extended-range industrial control, instrumentation, and automotive body electronics |
| Standby Current | 20 µA CMOS - enables ultra-low-power sleep modes in battery-backed or energy-harvesting systems |
Pinout & Package
AT28LV010-20JI is packaged in a 32-lead Plastic J-Leaded Chip Carrier (PLCC-32), JEDEC MS-016 AE compliant, with 1.27 mm pitch and surface-mount compatibility. Pin 1 is marked by index notch and corner chamfer per JEDEC standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A16 | Address Inputs | 17-bit address bus supporting full 128K-word addressing; A7–A16 define page boundaries for 128-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit write status monitoring |
| CE | Chip Enable | Active-low chip select; must be low for read/write access; high state forces output high-Z and inhibits writes |
| OE | Output Enable | Active-low output control; low with CE low enables read data; high disables outputs and inhibits writes |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; high state inhibits all write operations |
| NC / DC | No Connect / Don't Connect | Unbonded pins (e.g., Pin 1, Pin 32 in PLCC); must remain unconnected per design specification |
| VCC | Power Supply | 3.3V ±10% supply input; internal power-on delay prevents writes until stable >2.0V |
| GND | Ground Reference | Primary signal and power return; decoupling capacitor required within 10 mm of VCC/GND pair |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Mandatory 3-byte command sequence (AAh/55h/A0h) required before every write - prevents accidental overwrites during power transients or firmware faults |
| Automatic Page Write | Internal 128-byte latch and timer eliminate external timing logic; host can release bus after initial address/data load |
| DATA Polling & Toggle Bit | Dual, software-accessible write-complete indicators (I/O7 complement → true data; I/O6 toggling → stable) - no external wait-state circuitry needed |
| Hardware Write Inhibit | VCC power-on delay, noise-filtered WE/CE inputs, and multi-signal write gate (CE high/OE low/WE high) ensure robustness against EMI and brown-out conditions |
| JEDEC Byte-Wide Pinout | Pin-compatible with industry-standard EPROMs and SRAMs - enables direct replacement in legacy 8-bit memory sockets without PCB redesign |
| Extended Endurance Architecture | Internal error correction and optimized charge-pump design deliver 100,000K cycles - 10× higher than basic EEPROMs for high-write-rate logging |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
|
Use Scenario: Storing user-configurable I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers deployed in factory automation cabinets. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed at power-up and during runtime reconfiguration; requires guaranteed 10-year data retention at 70°C ambient. Use Value: AT28LV010-20JI's 20 µA standby current minimizes backup battery drain, while 200 ns read time enables fast boot initialization without CPU wait states. |
Use Scenario: Holding factory-calibrated sensor offsets and gain coefficients in portable diagnostic equipment subject to periodic recalibration and regulatory audit. IC Role / Device Role / Timing Role: Tamper-resistant calibration vault; write-protected via SDP and hardware inhibit to prevent unauthorized modification during service. Use Value: 100,000K endurance supports daily recalibration logs across 27 years; DATA polling eliminates need for fixed timeout delays in calibration firmware. |
| Automotive Body Control Module | Networking Equipment Bootloader Image |
|
Use Scenario: Storing seat/mirror position presets, lighting profiles, and door lock configurations in automotive BCMs operating across −40°C to +85°C. IC Role / Device Role / Timing Role: Automotive-grade nonvolatile memory interfaced directly to 8-bit MCU data bus; must survive repeated cold cranking voltage dips. Use Value: AT28LV010-20JI's VCC power-on delay and noise-filtered WE input prevent spurious writes during 4.5V–5.5V cranking transients; PLCC-32 package withstands thermal cycling. |
Use Scenario: Hosting immutable bootloader code and secure boot keys in enterprise switches/routers where firmware integrity is critical. IC Role / Device Role / Timing Role: Read-only execution source during cold start; write-protected except during authenticated firmware updates via dedicated service mode. Use Value: JEDEC byte-wide pinout allows direct substitution for legacy boot ROMs; 10 ms page write enables fast field updates without interrupting network uptime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C010-15PC | 5V-only supply, 150 ns access, PDIP-32 package, commercial temp only (0°C to 70°C) | Lacks low-voltage operation and industrial temp rating; no SDP - relies on VPP pin for write enable | Select only for legacy 5V systems where AT28LV010-20JI's 3.3V compatibility and enhanced protection are unnecessary |
| MX28LV160CBTI-20G | 3.3V, 200 ns, 16-Mbit capacity, TSOP-48, supports CFI command set and sector erase | Higher density and flash architecture; lacks true byte-write capability and requires block erasure before programming | Choose when scalable storage >1 Mbit is needed and system firmware can accommodate erase-before-write constraints |
Compared with AT28C010-15PC, AT28LV010-20JI enables direct integration into 3.3V domains with superior write safety; versus MX28LV160CBTI-20G, it offers true random-byte programmability without erase latency - critical for parameter logging and incremental updates.
Availability
AT28LV010-20JI is available at Aetrix Electronics and suitable for industrial control systems, medical diagnostics equipment, and automotive body electronics requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature performance.
Supply support for AT28LV010-20JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial, automotive, and IoT applications.
The AT28LV010 belongs to Atmel's low-voltage parallel EEPROM product line, designed specifically to replace 5V EPROMs and older EEPROMs in 3.3V systems while maintaining pin and function compatibility and adding robust write protection.
FAQ
What is the maximum operating temperature range for the AT28LV010-20JI?
The AT28LV010-20JI is rated for industrial temperature operation from −40°C to +85°C. This specification is confirmed in the Ordering Information table and DC Operating Range section of the datasheet, where "JI" suffix explicitly denotes the industrial grade. The device maintains full functionality-including 200 ns read access, 10 ms page write, and 20 µA standby current-across this entire range.
Does the AT28LV010-20JI require an external VPP voltage for programming?
No, the AT28LV010-20JI does not require an external VPP voltage. It performs all internal programming using charge-pump circuitry powered solely by the 3.3V VCC supply. This eliminates the need for high-voltage generation circuitry, simplifying board design and improving reliability compared to older 5V EEPROMs that required 12V VPP.
How is write completion detected on the AT28LV010-20JI?
Write completion on the AT28LV010-20JI is detected using either DATA polling on I/O7 (which returns complement of written data until completion, then true data) or the toggle-bit method on I/O6 (which toggles between 0 and 1 during programming and stabilizes upon completion). Both methods are accessible via standard read cycles and require no external components or timers.
Is the AT28LV010-20JI pin-compatible with standard SRAMs or EPROMs?
Yes, the AT28LV010-20JI uses a JEDEC-approved byte-wide pinout identical to industry-standard 128K × 8 SRAMs and EPROMs. Its PLCC-32 footprint matches devices like the 27C1001 and 62C1024, allowing direct socket replacement in existing 8-bit memory interfaces without layout changes - provided VCC and timing constraints are met.
What write protection mechanisms does the AT28LV010-20JI implement?
The AT28LV010-20JI implements dual-layer write protection: hardware-level inhibition via VCC power-on delay (~5 ms), noise filtering on WE/CE inputs (<15 ns rejection), and multi-signal gating (write blocked if CE high, OE low, or WE high); plus software-level protection requiring a mandatory three-byte SDP command sequence (AAh/55h/A0h) before every write operation.
AT28LV010-20JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28LV010-20JI FAQ
1.How can I place an order for AT28LV010-20JI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV010-20JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV010-20JI reliable?
The price and inventory of AT28LV010-20JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV010-20JI is usually 5 days.
3.What payment methods are accepted for AT28LV010-20JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV010-20JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV010-20JI?
AT28LV010-20JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV010-20JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV010-20JI?
For technical support, including AT28LV010-20JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV010-20JI requirements.
6.How does Aetrix verify that AT28LV010-20JI is sourced from the original manufacturer or authorized distributors?
All AT28LV010-20JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV010-20JI meets industry standards.
7.What is the process for return or replacement of AT28LV010-20JI?
All AT28LV010-20JI units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV010-20JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV010-20JI part is unused and in its original packaging.
Return procedure for AT28LV010-20JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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