Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

Microchip Technology AT28LV010-20JU-235

Name: AT28LV010-20JU-235
Brand: Microchip Technology
SKU: AT28LV010-20JU-235
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: AT28LV010-20JU-235

Manufacturer:: Microchip Technology

Category:: Memory

Package:: 32-LCC (J-Lead)

Datasheet:: AT28LV010-20JU-235.pdf

Description:: IC EEPROM 1MBIT PARALLEL 32PLCC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,248

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

AT28LV010-20JU-235 from Atmel is a 1 Mbit (128K × 8) low-voltage paged parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, 10 ms maximum page write cycle time, and operation from a single 3.3 V ± 10% supply. It supports 1–128-byte page writes with internal latching and automatic programming, and is rated for industrial temperature range (−40°C to +85°C).

For engineers reviewing the AT28LV010-20JU-235 datasheet, AT28LV010-20JU-235 pinout, AT28LV010-20JU-235 application, or AT28LV010-20JU-235 equivalent, key selection criteria include its CMOS standby current (20 µA), software/hardware data protection, DATA polling and toggle-bit write completion detection, and PLCC-32 packaging with JEDEC-compliant pin assignment.

Technical Context

The AT28LV010-20JU-235 implements a paged parallel EEPROM architecture with a 128-byte internal page register, enabling burst loading of up to 128 bytes before autonomous internal programming. Address and data are latched on WE/CE edges, and write initiation requires a three-byte Software Data Protection (SDP) command sequence - enabled at all times, unlike legacy 5 V EEPROMs.

Write completion is verified via dual methods: DATA polling on I/O7 (complement-to-data during write, true data after completion) and toggle-bit behavior on I/O6. The device uses advanced nonvolatile CMOS technology with built-in error correction, delivering 10⁵ write cycles endurance and 10-year data retention, and features hardware safeguards including VCC power-on delay, noise filtering (<15 ns pulse rejection), and CE/OE/WE write inhibit logic.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	1 Mbit (131,072 × 8), organized as 128K words × 8 bits - supports byte-level random access and page-aligned bulk writes.
Read Access Time	200 ns max - enables direct replacement of SRAM in legacy 8-bit bus systems without wait-state insertion.
Page Write Cycle Time	10 ms max - allows efficient firmware patching or configuration updates without system freeze longer than 10 ms per 128-byte block.
V_CC Supply Range	3.3 V ± 10% - compatible with modern low-voltage microcontroller buses and eliminates need for level-shifting in 3.3 V systems.
Standby Current	20 µA CMOS - reduces quiescent power in battery-backed or always-on industrial control modules.
Endurance	10⁵ write cycles - sufficient for field-upgradable calibration tables, event logs, or parameter storage in embedded instrumentation.
Data Retention	10 years at 85°C - ensures long-term reliability in unattended industrial monitoring equipment.

Pinout & Package

AT28LV010-20JU-235 is packaged in a 32-lead Plastic J-Leaded Chip Carrier (PLCC), JEDEC MS-016 compliant, with 1.27 mm pitch and 12.32 mm × 14.86 mm body size. Pin 1 identifier is a corner chamfer; leads are gull-wing with 0.102 mm max coplanarity.

Pin/Terminal	Circuit Role	Design Meaning
A0–A16	Address Inputs	17-bit address bus supporting full 128K-word addressing; A7–A16 define page boundaries for 128-byte writes.
I/O0–I/O7	Bidirectional Data Bus	8-bit parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit status indication during writes.
CE	Chip Enable	Active-low chip select; must remain de-asserted ≥50 ns between reads to prevent data corruption.
OE	Output Enable	Active-low output control; enables high-impedance state when high to prevent bus contention.
WE	Write Enable	Active-low write strobe; falling edge latches address/data; rising edge initiates internal programming if SDP sequence completed.
V_CC	Power Supply	3.3 V ± 10% input; includes internal 5 ms power-on delay before write circuitry activation.
GND	Ground	Reference for all I/O and internal logic; decoupling capacitor required within 10 mm of V_CC/GND pins.
NC / DC	No Connect / Don't Connect	Unbonded or unused pins; must be left floating - no external connection permitted.

Key Features

Feature	Design Value
Software Data Protection (SDP)	Three-byte command sequence required before every write - prevents accidental overwrites during power transitions or noise events.
Automatic Page Programming	Internal control timer executes full 128-byte write after final data latch - frees host bus for other tasks during 10 ms internal cycle.
DATA Polling & Toggle Bit	Dual asynchronous write-complete detection on I/O7 and I/O6 - eliminates need for fixed delays or external timers in host firmware.
Hardware Write Inhibit	VCC power-on delay, OE/CE/WE logic-level inhibition, and <15 ns noise filtering - ensures robustness in electrically noisy industrial environments.
Green Packaging	Pb/halide-free PLCC-32 - complies with RoHS Directive 2011/65/EU and supports lead-free reflow profiles.

Applications

Industrial PLC Configuration Storage	Medical Device Calibration Data
Use Scenario: Storing user-configurable I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via 8-bit parallel bus; retains settings across power cycles and supports field updates via serial host interface. Use Value: 200 ns read access enables real-time parameter lookup during scan cycles; 10⁵ endurance supports daily recalibration logging over 10+ years.	Use Scenario: Holding factory-calibrated sensor offsets, gain coefficients, and diagnostic history in portable patient monitors and infusion pumps. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter store with hardware/software write protection to meet IEC 62304 safety requirements. Use Value: 20 µA standby current extends battery life in battery-operated devices; 10-year data retention ensures calibration validity throughout product lifetime.
Telecom Line Card Firmware Patching	Automotive Body Control Module NVM
Use Scenario: Applying minor firmware patches or protocol stack updates to telecom line cards without full flash reprogramming or board removal. IC Role / Device Role / Timing Role: Paged EEPROM used for hot-swappable update storage; host CPU loads patch into page buffer then triggers atomic write. Use Value: 10 ms page write time minimizes service interruption; DATA polling allows deterministic timing for patch validation before reboot.	Use Scenario: Storing vehicle-specific configuration (e.g., door lock logic, mirror position presets, lighting profiles) in automotive BCMs operating across −40°C to +85°C. IC Role / Device Role / Timing Role: Industrial-grade NVM interfaced directly to 8-bit microcontroller bus; withstands automotive load dump and cold-crank conditions. Use Value: −40°C to +85°C rating matches under-hood thermal envelope; hardware write inhibit prevents corruption during ignition transients.

Industrial PLC Configuration Storage

Medical Device Calibration Data

Use Scenario: Storing user-configurable I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers deployed in factory automation.

IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via 8-bit parallel bus; retains settings across power cycles and supports field updates via serial host interface.

Use Value: 200 ns read access enables real-time parameter lookup during scan cycles; 10⁵ endurance supports daily recalibration logging over 10+ years.

Use Scenario: Holding factory-calibrated sensor offsets, gain coefficients, and diagnostic history in portable patient monitors and infusion pumps.

IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter store with hardware/software write protection to meet IEC 62304 safety requirements.

Use Value: 20 µA standby current extends battery life in battery-operated devices; 10-year data retention ensures calibration validity throughout product lifetime.

Telecom Line Card Firmware Patching

Automotive Body Control Module NVM

Use Scenario: Applying minor firmware patches or protocol stack updates to telecom line cards without full flash reprogramming or board removal.

IC Role / Device Role / Timing Role: Paged EEPROM used for hot-swappable update storage; host CPU loads patch into page buffer then triggers atomic write.

Use Value: 10 ms page write time minimizes service interruption; DATA polling allows deterministic timing for patch validation before reboot.

Use Scenario: Storing vehicle-specific configuration (e.g., door lock logic, mirror position presets, lighting profiles) in automotive BCMs operating across −40°C to +85°C.

IC Role / Device Role / Timing Role: Industrial-grade NVM interfaced directly to 8-bit microcontroller bus; withstands automotive load dump and cold-crank conditions.

Use Value: −40°C to +85°C rating matches under-hood thermal envelope; hardware write inhibit prevents corruption during ignition transients.

Equivalent & Alternatives

The following parts are listed as comparable options for similar paged parallel EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AT28C010-15PU	5 V-only supply; 150 ns access; no SDP; 32-pin PDIP package	Lacks low-voltage operation and software write protection; unsuitable for 3.3 V systems or safety-critical updates	Select only for legacy 5 V designs where SDP and 3.3 V compatibility are not required.
M95M01-RDW6TP	1 Mbit SPI EEPROM; 5 ms write time; 3.3 V supply; SO8 package	Serial interface reduces pin count but increases write latency vs. parallel bus; no native DATA polling	Prefer for space-constrained designs accepting SPI overhead; avoid when deterministic parallel-bus timing is critical.

Compared with AT28LV010-20JU-235, AT28C010-15PU lacks voltage flexibility and data protection, while M95M01-RDW6TP trades parallel speed and polling capability for footprint reduction - making AT28LV010-20JU-235 optimal for deterministic, secure, 3.3 V parallel-bus NVM in industrial control.

Availability

AT28LV010-20JU-235 is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, telecom line cards, and automotive body control modules requiring stable component supply, long-lifecycle support, and RoHS-compliant green packaging.

Supply support for AT28LV010-20JU-235 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor innovator known for nonvolatile memory, microcontrollers, and secure authentication ICs, with deep expertise in EEPROM reliability and industrial-grade process technology.

The AT28LV010 product line was designed specifically for 3.3 V embedded systems needing byte-addressable, page-write-capable EEPROM with deterministic timing, robust write protection, and extended temperature operation - targeting industrial, medical, and telecom infrastructure.

FAQ

What is the correct power-up sequence for AT28LV010-20JU-235 to ensure reliable write operations?

The AT28LV010-20JU-235 incorporates an internal VCC power-on delay: once VCC reaches 2.0 V (typical), the device automatically waits ~5 ms before enabling write circuitry. No external reset sequencing is required - simply stabilize VCC within 3.3 V ± 10% and allow ≥5 ms before issuing the SDP command sequence. This ensures internal logic is fully initialized before any write attempt, preventing corruption during brown-out recovery. Always verify VCC ramp rate meets datasheet minimum slew rate specifications.

Does AT28LV010-20JU-235 support true byte-write operations, or is it page-only?

The AT28LV010-20JU-235 supports both single-byte and multi-byte writes within a 128-byte page boundary defined by A7–A16. While the internal programming mechanism operates on the entire latched page, the host may write 1 to 128 bytes per operation - only addressed bytes are modified; others retain prior values. This avoids unnecessary wear on unmodified locations. Each byte must be loaded within 150 µs of the previous one (tBLC) to remain in the same page write cycle.

How does the Software Data Protection (SDP) feature work on AT28LV010-20JU-235, and can it be disabled?

The AT28LV010-20JU-235 implements SDP as a mandatory three-byte command sequence (0xAA to address 0x5555, 0x55 to 0x2AAA, 0xA0 to 0x5555) preceding every write - it is enabled at all times and cannot be permanently disabled. To receive units with SDP temporarily disabled for development, Atmel offered SL319-marked variants; however, AT28LV010-20JU-235 itself ships with SDP active. This design prevents accidental writes during power transitions or noise events.

What are the timing constraints for verifying write completion using DATA polling on AT28LV010-20JU-235?

During a write cycle on AT28LV010-20JU-235, reading the last written byte returns the complement of that data on I/O7. Once true data appears on I/O7, the write is complete. Polling may begin immediately after initiating the write - no minimum delay is required. However, the host must observe tDH (10 ns) and tOEH (10 ns) hold times per AC specs, and avoid violating tCEPH (50 ns CE pulse high time) during polling reads to ensure signal integrity.

Is AT28LV010-20JU-235 pin-compatible with standard 28-series EEPROMs like AT28C256?

No, AT28LV010-20JU-235 is not pin-compatible with AT28C256 or other 5 V 28-series EEPROMs. Although both use 32-pin packages, AT28LV010-20JU-235 follows JEDEC byte-wide pinout with dedicated A0–A16 and I/O0–I/O7 assignments, whereas AT28C256 uses different address/data multiplexing and control pin placement. The PLCC-32 footprint is identical, but signal routing and PCB layout must be redesigned to match AT28LV010-20JU-235's pin functions.

AT28LV010-20JU-235 Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 32-LCC (J-Lead)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 1Mbit

Memory Organization:: 128K x 8

Memory Interface:: Parallel

Clock Frequency:: -

Write Cycle Time - Word, Page:: 10ms

Access Time:: 200 ns

Voltage - Supply:: 3V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C (TC)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 32-PLCC (13.97x11.43)

AT28LV010-20JU-235 FAQ

1.How can I place an order for AT28LV010-20JU-235 through Aetrix?

Please submit a Request for Quotation (RFQ) for AT28LV010-20JU-235 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT28LV010-20JU-235 reliable?

The price and inventory of AT28LV010-20JU-235 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV010-20JU-235 is usually 5 days.

3.What payment methods are accepted for AT28LV010-20JU-235?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV010-20JU-235 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT28LV010-20JU-235?

AT28LV010-20JU-235 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT28LV010-20JU-235 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT28LV010-20JU-235?

For technical support, including AT28LV010-20JU-235 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV010-20JU-235 requirements.

6.How does Aetrix verify that AT28LV010-20JU-235 is sourced from the original manufacturer or authorized distributors?

All AT28LV010-20JU-235 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV010-20JU-235 meets industry standards.

7.What is the process for return or replacement of AT28LV010-20JU-235?

All AT28LV010-20JU-235 units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV010-20JU-235, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT28LV010-20JU-235 part is unused and in its original packaging.

Return procedure for AT28LV010-20JU-235:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…