Microchip Technology AT28LV010-20JU-630
- Part No.:
- AT28LV010-20JU-630
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28LV010-20JU-630.pdf
- Description:
- IC EEPROM 1MBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:750
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Product details
Overview
AT28LV010-20JU-630 from Microchip Technology (formerly Atmel) is a 1 Mbit (128K × 8) low-voltage paged parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, and single 3.3 V ±10% supply operation. It supports 1–128-byte page writes with internal latching and automatic programming, enabling embedded system firmware storage, configuration retention, and boot code storage in industrial controllers.
For engineers reviewing the AT28LV010-20JU-630 datasheet, AT28LV010-20JU-630 pinout, AT28LV010-20JU-630 application, or AT28LV010-20JU-630 equivalent, key selection criteria include its 20 µA CMOS standby current, hardware/software data protection, DATA polling and toggle-bit write completion detection, and industrial temperature range (−40°C to +85°C).
Technical Context
The AT28LV010-20JU-630 operates as a drop-in SRAM-compatible nonvolatile memory: reads require CE and OE low with WE high; writes require a three-byte Software Data Protection (SDP) command sequence before each page or byte operation. Its internal 128-byte page register latches address and data on falling WE/CE edges, freeing the bus during internal programming.
Write completion is verified via I/O7 DATA polling (complement-to-true transition) or I/O6 toggle-bit behavior, both usable at any point during the ≤10 ms internal write cycle. Hardware protection includes VCC power-on delay (~5 ms), noise filtering (<15 ns pulse rejection), and write inhibit via OE low, CE high, or WE high states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1 Mbit (131,072 × 8), organized for direct byte-addressable access without external decoding logic |
| Read Access Time | 200 ns - enables real-time firmware fetch in microcontroller boot loaders and FPGA configuration storage |
| Page Write Cycle | ≤10 ms - supports rapid field-upgradable parameter sets in programmable logic controllers |
| Supply Voltage | 3.3 V ±10% - compatible with modern low-voltage digital systems without level-shifting circuitry |
| Standby Current | 20 µA - minimizes quiescent power in battery-backed industrial sensors and remote I/O modules |
| Data Retention | 10 years - ensures long-term reliability of calibration data and device identity in deployed equipment |
| Endurance | 10⁵ write cycles - sufficient for daily firmware updates over 27+ years in maintenance-critical infrastructure |
Pinout & Package
AT28LV010-20JU-630 is packaged in a 32-lead Plastic J-Leaded Chip Carrier (PLCC), JEDEC MS-016 compliant, with 1.27 mm pitch and 12.32 mm × 14.86 mm body size. Pin 1 identifier is a corner chamfer; leads are gull-wing with 0.102 mm max coplanarity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A16 | Address Inputs | 17-bit address bus supporting full 128K-word addressing; A7–A16 define page boundaries for 128-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | True 8-bit parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit write status indication |
| CE | Chip Enable | Active-low global enable; must remain de-asserted ≥50 ns between reads to prevent data corruption |
| OE | Output Enable | Active-low output control; dual-line (CE + OE) gating prevents bus contention in shared-memory systems |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; rising edge initiates internal programming timer |
| VCC | Power Supply | 3.3 V ±10% input; internal power-on delay (~5 ms) prevents spurious writes during power ramp-up |
| GND | Ground Reference | Common return path for all signals; decoupling capacitor placement critical near VCC/GND pins |
| NC / DC | No Connect / Don't Connect | Unbonded pins; must be left floating per datasheet - no tie-high/tie-low or routing allowed |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Three-byte command sequence (AAh→55h→A0h) required before every write - prevents accidental firmware overwrite during brown-out or reset |
| Page Write Architecture | 128-byte internal latch allows burst loading of configuration blocks without CPU bus occupancy during programming |
| DATA Polling & Toggle Bit | Dual asynchronous write-completion detection methods - eliminates need for fixed delays or external timers in host firmware |
| Hardware Write Inhibit | VCC power-on delay, noise filtering, and multi-signal gating (CE/OE/WE) ensure robustness in electrically noisy industrial environments |
| Green Packaging | Pb/halide-free PLCC package - meets RoHS Directive 2011/65/EU and IPC/JEDEC J-STD-609A Class 1 moisture sensitivity |
Applications
| Industrial PLC Configuration Storage | FPGA Bitstream Backup |
|---|---|
Use Scenario: Storing user-defined I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers operating in harsh factory environments. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during cold start and runtime reconfiguration; retains data across power loss. Use Value: 20 µA standby current extends battery backup life; 10⁵ endurance supports weekly parameter updates over 27+ years. | Use Scenario: Holding fallback configuration bitstreams for Xilinx Spartan or Lattice MachXO FPGAs used in telecom base station control cards. IC Role / Device Role / Timing Role: Parallel boot memory mapped to FPGA's configuration interface; 200 ns read access enables sub-µs startup latency. Use Value: JEDEC byte-wide pinout simplifies PCB layout; 3.3 V compatibility eliminates level shifters in modern FPGA power domains. |
| Medical Device Calibration Data | Automated Test Equipment (ATE) Fixture ID |
Use Scenario: Storing sensor calibration coefficients, linearity corrections, and serial-number-linked traceability data in portable diagnostic instruments. IC Role / Device Role / Timing Role: Secure, tamper-resistant nonvolatile memory with hardware/software write protection to meet IEC 62304 safety requirements. Use Value: SDP command sequence prevents unauthorized calibration changes; 10-year data retention satisfies FDA 21 CFR Part 11 record-keeping mandates. | Use Scenario: Encoding fixture-specific test profiles, probe compensation values, and revision history in semiconductor ATE handler interfaces. IC Role / Device Role / Timing Role: Read/write configuration store accessed by test controller during fixture setup and calibration cycles. Use Value: Page write capability allows atomic update of full fixture profile (≤128 bytes) in ≤10 ms - minimizing test downtime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C010-15PU | 5 V-only supply; 150 ns access; no SDP; 10⁴ endurance; DIP-32 package | Lacks low-voltage operation and advanced write protection; unsuitable for 3.3 V systems or safety-critical updates | Select only for legacy 5 V designs where voltage compatibility and cost outweigh endurance and security needs |
| MN63F1002BKP | 3.3 V operation; SPI interface; 100 MHz clock; 5 ms page write; SOIC-8 package | Serial interface reduces pin count but increases software overhead; no SRAM-like parallel access | Choose when board space is constrained and host MCU has SPI peripherals; avoid when deterministic <200 ns read timing is required |
Compared with AT28C010-15PU and MN63F1002BKP, the AT28LV010-20JU-630 uniquely delivers 3.3 V parallel EEPROM functionality with integrated SDP, 200 ns read speed, and industrial temperature support - making it optimal for new designs requiring SRAM-equivalent nonvolatile storage with robust data integrity.
Availability
AT28LV010-20JU-630 is available at Aetrix Electronics and suitable for industrial PLCs, FPGA configuration backup, medical calibration storage, and automated test equipment requiring stable component supply and long-lifecycle assurance.
Supply support for AT28LV010-20JU-630 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains its legacy EEPROM product lines with full documentation, longevity commitments, and manufacturing continuity.
The AT28LV010 series was designed specifically for industrial and medical applications requiring reliable, low-power, parallel-interface nonvolatile memory with enhanced write protection and extended data retention - not general-purpose consumer storage.
FAQ
What is the maximum page write size supported by the AT28LV010-20JU-630?
The AT28LV010-20JU-630 supports up to 128 bytes per page write operation. This is enabled by its internal 128-byte page register, which latches address and data on the falling edge of WE or CE. All bytes written in a single page operation must reside within the same 128-byte boundary defined by address bits A7–A16, and the page address must remain constant across successive WE transitions.
Does the AT28LV010-20JU-630 require external components for basic read/write operation?
No, the AT28LV010-20JU-630 operates like a Static RAM for both read and write cycles and requires no external components for core functionality. Its internal control timer manages programming duration, and built-in DATA polling and toggle-bit features eliminate the need for external wait-state generators or timers. Only standard decoupling capacitors (0.1 µF ceramic near VCC/GND) are recommended per datasheet guidelines.
How does the Software Data Protection (SDP) feature work on the AT28LV010-20JU-630?
The AT28LV010-20JU-630 implements industry-standard SDP that is always enabled. Every write operation must begin with a precise three-byte command sequence: write 0xAA to address 0x5555, then 0x55 to address 0x2AAA, then 0xA0 to address 0x5555. Only after this sequence is completed will subsequent writes to any address be accepted. Attempts without the sequence trigger internal timers but write no data, preserving memory integrity.
What is the purpose of the NC and DC pins on the AT28LV010-20JU-630 PLCC package?
The NC (No Connect) and DC (Don't Connect) pins on the AT28LV010-20JU-630 are unconnected die bond pads. They must remain electrically floating - no pull-up, pull-down, or routing is permitted. The datasheet explicitly prohibits connecting these pins to VCC, GND, or any signal, as doing so may cause unpredictable behavior or damage due to internal floating node coupling or ESD path disruption.
Can the AT28LV010-20JU-630 be used in automotive applications?
No, the AT28LV010-20JU-630 is specified only for industrial temperature range (−40°C to +85°C) and is not qualified for automotive use. Atmel/Microchip explicitly states in its datasheet disclaimer that "Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life," including automotive safety-critical systems. For AEC-Q100 qualified alternatives, consult Microchip's automotive EEPROM portfolio separately.
AT28LV010-20JU-630 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28LV010-20JU-630 FAQ
1.How can I place an order for AT28LV010-20JU-630 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV010-20JU-630 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV010-20JU-630 reliable?
The price and inventory of AT28LV010-20JU-630 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV010-20JU-630 is usually 5 days.
3.What payment methods are accepted for AT28LV010-20JU-630?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV010-20JU-630 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV010-20JU-630?
AT28LV010-20JU-630 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV010-20JU-630 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV010-20JU-630?
For technical support, including AT28LV010-20JU-630 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV010-20JU-630 requirements.
6.How does Aetrix verify that AT28LV010-20JU-630 is sourced from the original manufacturer or authorized distributors?
All AT28LV010-20JU-630 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV010-20JU-630 meets industry standards.
7.What is the process for return or replacement of AT28LV010-20JU-630?
All AT28LV010-20JU-630 units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV010-20JU-630, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV010-20JU-630 part is unused and in its original packaging.
Return procedure for AT28LV010-20JU-630:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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