Microchip Technology AT28LV010-20TC

Overview

AT28LV010-20TC from Atmel is a 1-Mbit (128K × 8) single-supply 3.3V paged parallel EEPROM with 200 ns read access time, JEDEC-standard byte-wide pinout, and hardware/software data protection. It operates across commercial temperature range (0°C to 70°C), supports 1–128-byte page writes, and delivers 15 mA active current with 20 µA CMOS standby current for embedded nonvolatile storage in microcontroller systems.

For engineers reviewing the AT28LV010-20TC datasheet, AT28LV010-20TC pinout, AT28LV010-20TC application, or AT28LV010-20TC equivalent, key selection criteria include its 200 ns read timing, 10 ms max page write cycle, 100,000K endurance rating, DATA polling/Toggle Bit write completion detection, and compatibility with standard SRAM-like bus interfaces without external timing logic.

Technical Context

The AT28LV010-20TC implements a paged write architecture with a 128-byte internal latching register, enabling burst loading of up to 128 bytes before initiating autonomous internal programming. Address and data are latched on WE/CE edges, and write operations require the three-byte Software Data Protection (SDP) command sequence prior to each page or byte write.

It features dual write-completion detection: DATA polling via I/O7 (complement → true data transition) and Toggle Bit behavior on I/O6 (toggling ceases upon completion). The device uses advanced CMOS nonvolatile technology with built-in error correction for 10-year data retention and 100,000K write cycles, and includes 128 bytes of dedicated identification EEPROM.

Key Specifications

Pinout & Package

AT28LV010-20TC is packaged in a 32-lead Plastic Thin Small Outline Package (TSOP), JEDEC MO-142 DD compliant, with 0.5 mm lead pitch and body dimensions 11.8 × 10.0 mm. Pin 1 marked by index notch; pins arranged in two rows, 16 per side.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar paged parallel EEPROM applications.

Compared with AT28C010-15PC, the AT28LV010-20TC enables lower-system-power operation and stronger write security; versus MN63F1000BGP, it preserves existing SRAM-style bus architecture but occupies more PCB area and lacks serial flexibility.

Availability

AT28LV010-20TC is available at Aetrix Electronics and suitable for industrial PLC configuration storage, medical device calibration data retention, and telecom bootloader applications requiring stable component supply, long-life data integrity, and drop-in JEDEC-compatible packaging.

Supply support for AT28LV010-20TC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs, with a legacy of high-reliability industrial and automotive devices.

The AT28LV010 belongs to Atmel's low-voltage parallel EEPROM product line, designed specifically for seamless migration from 5 V EPROM/SRAM-based systems to 3.3 V embedded platforms while preserving board layout and firmware interface simplicity.

FAQ

What is the guaranteed read access time for AT28LV010-20TC?

The AT28LV010-20TC guarantees a maximum read access time of 200 ns under commercial temperature conditions (0°C to 70°C) and 3.3 V ± 5% supply. This specification is tested and characterized per AC Read Characteristics in the official Atmel datasheet Rev. 0395B–10/98, and applies to all valid address-to-output paths including tACC and tCE timing parameters. The "20" in the part number explicitly denotes this 200 ns speed grade.

Does AT28LV010-20TC require external hardware for write protection?

No, AT28LV010-20TC integrates both hardware- and software-based write protection. Hardware features include VCC power-on delay (~5 ms), automatic write inhibit when CE is high or OE is low, and a 15 ns noise filter on WE/CE inputs. Software protection mandates the three-byte SDP command sequence (AAh/55h/A0h) before any write - eliminating need for external WP pins or discrete logic.

How does write completion detection work on AT28LV010-20TC?

The AT28LV010-20TC provides two independent, asynchronous methods: DATA polling monitors I/O7 - it outputs the complement of the last written byte until completion, then switches to true data; Toggle Bit monitors I/O6 - it toggles between 0 and 1 during programming and stops toggling once complete. Both methods allow firmware to poll without fixed timeouts and are usable at any point during the write cycle.

What package type is used for AT28LV010-20TC?

AT28LV010-20TC uses a 32-lead Plastic Thin Small Outline Package (TSOP), designated as package code "32T" per Atmel's ordering information. Its JEDEC MO-142 DD outline measures 11.8 mm × 10.0 mm with 0.5 mm lead pitch, and features gull-wing leads suitable for surface-mount reflow assembly. Pin 1 is identified by a notch in the package body.

Is AT28LV010-20TC compatible with standard SRAM bus timing?

Yes, AT28LV010-20TC is designed for SRAM-like interface: reads occur when CE and OE are low and WE is high, with outputs driven directly onto the data bus. No external address latches, clocks, or handshaking signals are required. Its 200 ns access time and JEDEC byte-wide pinout enable direct replacement of 128K×8 SRAMs such as the 628128 in existing designs without timing or layout changes.