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Microchip Technology AT28LV010-20TU-235
- Part No.:
- AT28LV010-20TU-235
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-TFSOP (0.724", 18.40mm Width)
- Datasheet:
-
AT28LV010-20TU-235.pdf
- Description:
- IC EEPROM 1MBIT PARALLEL 32TSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,566
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Product details
Overview
AT28LV010-20TU-235 from Atmel is a 1 Mbit (128K × 8) low-voltage paged parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, 3.3 V ± 10% supply operation, and industrial temperature range (–40°C to +85°C). It supports automatic 1–128-byte page writes with internal latching and DATA polling for write completion detection, used in firmware storage and configuration retention in embedded controllers.
For engineers reviewing the AT28LV010-20TU-235 datasheet, AT28LV010-20TU-235 pinout, AT28LV010-20TU-235 application, or AT28LV010-20TU-235 equivalent, key selection criteria include its 200 ns read timing, 10 ms max page write cycle, CMOS standby current of 20 µA, hardware/software data protection, and TSOP-32 packaging for space-constrained PCB layouts.
Technical Context
The AT28LV010-20TU-235 operates as a drop-in SRAM-compatible nonvolatile memory: reads require CE and OE low with WE high; writes use software data protection (SDP) command sequence (0x5555/0x2AAA/0x5555) before each page load. Address and data are latched on WE/CE edges, enabling bus release during internal programming.
It implements dual write-completion detection: DATA polling on I/O7 (complement → true data transition) and toggle-bit behavior on I/O6. Page addressing is constrained by A7–A16 (page base), while A0–A6 select bytes within the 128-byte page - no wraparound or cross-page writes permitted.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 1 Mbit (131,072 × 8), organized as 128K words × 8 bits - supports full firmware image or parameter bank storage in microcontroller systems. |
| Read Access Time | 200 ns maximum - enables direct replacement of fast SRAM in boot code or configuration lookup tables without wait-state insertion. |
| Page Write Cycle | 10 ms maximum - allows burst programming of up to 128 bytes per cycle, reducing host CPU overhead vs. byte-by-byte writes. |
| Supply Voltage | 3.3 V ± 10% - compatible with modern low-voltage logic families and eliminates need for 5 V rails in mixed-signal designs. |
| Standby Current | 20 µA typical CMOS - suitable for battery-backed or energy-sensitive applications such as remote sensors and portable instrumentation. |
| Data Retention | 10 years minimum - ensures long-term reliability for field-deployed equipment without periodic refresh or reprogramming. |
| Endurance | 10⁵ write/erase cycles - sufficient for infrequent configuration updates, calibration storage, or event logging in industrial control units. |
Pinout & Package
AT28LV010-20TU-235 is packaged in a 32-lead Plastic Thin Small Outline Package (TSOP, Type I, 8 mm × 20 mm), compliant with JEDEC MO-142 BD. Pin 1 is marked by a beveled corner; package is green (Pb/halide-free).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A16 | Address Inputs | 17-bit address bus supporting full 128K-word addressing; A7–A16 define 128-byte page boundaries for write operations. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; I/O7 provides DATA polling status; I/O6 provides toggle-bit write-complete indication. |
| CE | Chip Enable | Active-low chip select; must remain asserted ≥50 ns during reads to avoid data corruption; inhibits writes when high. |
| OE | Output Enable | Active-low output control; used with CE to manage bus contention; must be high during write cycles. |
| WE | Write Enable | Active-low write strobe; latches address/data on falling edge; initiates SDP command validation and page programming. |
| VCC | Power Supply | 3.3 V ± 10% input; includes internal power-on delay (~5 ms) to prevent spurious writes during power ramp-up. |
| GND | Ground Reference | Signal and power ground reference; decoupling capacitor required near VCC pin for stable read/write timing. |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Always-enabled 3-byte command sequence (0x5555/0x2AAA/0x5555) required before every write - prevents accidental overwrites during power transients or firmware bugs. |
| Automatic Page Write | Internal 128-byte latch and timer eliminate host-side timing management; host can release bus after loading first byte and return later for polling. |
| DATA Polling & Toggle Bit | Dual asynchronous write-complete detection methods - allows flexible host polling strategy without fixed delays or external interrupts. |
| JEDEC Byte-Wide Pinout | Pin-compatible with industry-standard EPROM/EEPROM sockets and logic families - simplifies migration from legacy 27Cxxx or 28Cxxx devices. |
| Industrial Temperature Range | –40°C to +85°C operation - validated for deployment in motor drives, PLC modules, and outdoor telemetry hardware without derating. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Retention |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation cabinets. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed at power-up and updated only during commissioning or maintenance mode. Use Value: Ensures deterministic boot behavior and preserves settings across 10+ year service life without battery backup or external supervision. |
Use Scenario: Holding sensor offset/gain coefficients and regulatory compliance logs in portable ultrasound or infusion pump controllers. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter vault with hardware write inhibit and SDP enforcement during field calibration. Use Value: Meets IEC 62304 Class B software requirements for data integrity and eliminates risk of corrupted calibration due to brown-out or reset glitches. |
| Telecom Line Card Boot Firmware | Automotive Body Control Module Settings |
Use Scenario: Storing boot loader images and FPGA configuration bitstreams in carrier-grade DSLAM or OLT line cards operating in telecom central offices. IC Role / Device Role / Timing Role: Parallel memory mapped at fixed address space; read during cold start with 200 ns latency to minimize boot time. Use Value: Eliminates need for serial flash + decompression, reducing BOM count and improving first-instruction timing predictability. |
Use Scenario: Retaining user preferences (window position, mirror angle, lighting profiles) and diagnostic trouble codes in automotive BCMs. IC Role / Device Role / Timing Role: Low-power EEPROM accessed via microcontroller GPIO-banged parallel interface during sleep/wake transitions. Use Value: Achieves <20 µA standby draw while preserving state across ignition cycles - critical for meeting ISO 16750-2 quiescent current limits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C010-15PU | 5 V-only supply; 150 ns access; PLCC-32; no SDP - relies on VCC threshold and hardware write protect only. | Lacks low-voltage compatibility and robust software protection; requires separate 5 V rail and external lock bits. | Choose only if legacy 5 V system architecture prohibits voltage translation and firmware cannot implement SDP-equivalent safeguards. |
| MN63F1002BGP | 3.3 V supply; 120 ns access; TSOP-32; SPI interface - serial protocol, not parallel; no page write latch or DATA polling. | Requires SPI controller resource and software driver stack; incompatible pinout and timing model for SRAM-mapped systems. | Select when board space is extremely constrained and host MCU has spare SPI peripherals; not a functional substitute for parallel bus integration. |
Compared with AT28LV010-20TU-235, AT28C010-15PU trades lower voltage flexibility and weaker data protection for faster read speed in 5 V environments, while MN63F1002BGP sacrifices parallel bus simplicity and real-time write status feedback for reduced pin count and footprint - neither offers pin-to-pin or functional equivalence.
Availability
AT28LV010-20TU-235 is available at Aetrix Electronics and suitable for industrial PLCs, medical calibration systems, telecom line cards, and automotive body control modules requiring stable component supply, long-life data retention, and JEDEC-compliant parallel EEPROM functionality.
Supply support for AT28LV010-20TU-235 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs, with deep expertise in embedded flash and EEPROM process technologies.
The AT28LV010 product line was designed for reliable, low-voltage firmware and configuration storage in industrial and communications equipment where SRAM-like interface simplicity and long-term data integrity are mandatory.
FAQ
What is the correct software data protection (SDP) sequence for AT28LV010-20TU-235?
The AT28LV010-20TU-235 requires a precise three-step SDP command sequence before any write: write 0xAA to address 0x5555, then 0x55 to address 0x2AAA, then 0xA0 to address 0x5555. This sequence must precede every page or byte write. The AT28LV010-20TU-235 will ignore all subsequent data writes until this sequence is correctly issued, and no data is stored during the command phase itself.
Can AT28LV010-20TU-235 be used as a direct replacement for standard SRAM in existing designs?
AT28LV010-20TU-235 supports SRAM-like read access with identical CE/OE/WE timing, but write operations differ fundamentally: it requires SDP commands, page-aligned addressing, and polling for completion. While read cycles are drop-in compatible, write firmware must be modified to handle AT28LV010-20TU-235's protected page-write protocol and status detection - it is not a transparent SRAM substitute for write-intensive applications.
What is the maximum number of bytes that can be written in a single AT28LV010-20TU-235 page write cycle?
The AT28LV010-20TU-235 supports writing 1 to 128 bytes per page write cycle. All bytes must reside within the same 128-byte page, defined by address bits A7–A16. The device internally latches the entire page load and executes the programming operation autonomously. Attempting to write across page boundaries - even with valid A0–A6 addressing - will result in incomplete or corrupted data in the AT28LV010-20TU-235.
How does DATA polling work on AT28LV010-20TU-235, and which pin indicates completion?
During a write cycle, reading the last written byte from AT28LV010-20TU-235 returns the complement of that data on I/O7. When the write completes, I/O7 outputs the true (non-inverted) value. This transition - from complement to true data - signals write completion. The AT28LV010-20TU-235 allows polling at any time during the write, eliminating fixed timeout delays in host firmware.
Is AT28LV010-20TU-235 RoHS compliant and lead-free?
Yes, AT28LV010-20TU-235 uses green (Pb/halide-free) packaging per ordering information section 23.1. It complies with RoHS Directive 2011/65/EU and is manufactured without lead, brominated flame retardants, or other restricted substances. The TSOP-32 package carries no exemptions and is suitable for environmentally regulated end equipment including medical and industrial products.
AT28LV010-20TU-235 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-TFSOP (0.724", 18.40mm Width)
- Packaging:
- Cut Tape (CT)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-TSOP
AT28LV010-20TU-235 FAQ
1.How can I place an order for AT28LV010-20TU-235 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV010-20TU-235 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV010-20TU-235 reliable?
The price and inventory of AT28LV010-20TU-235 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV010-20TU-235 is usually 5 days.
3.What payment methods are accepted for AT28LV010-20TU-235?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV010-20TU-235 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV010-20TU-235?
AT28LV010-20TU-235 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV010-20TU-235 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV010-20TU-235?
For technical support, including AT28LV010-20TU-235 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV010-20TU-235 requirements.
6.How does Aetrix verify that AT28LV010-20TU-235 is sourced from the original manufacturer or authorized distributors?
All AT28LV010-20TU-235 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV010-20TU-235 meets industry standards.
7.What is the process for return or replacement of AT28LV010-20TU-235?
All AT28LV010-20TU-235 units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV010-20TU-235, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV010-20TU-235 part is unused and in its original packaging.
Return procedure for AT28LV010-20TU-235:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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