Microchip Technology AT28LV256-25SI
- Part No.:
- AT28LV256-25SI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28LV256-25SI.pdf
- Description:
- IC EEPROM 256KBIT PAR 28SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,189
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Product details
Overview
AT28LV256-25SI from Atmel is a 256 Kbit (32K × 8) parallel EEPROM operating from a single 3.0V–3.6V supply, featuring 250 ns read access time, 10 ms maximum page write cycle time, 15 mA active current, and JEDEC-standard byte-wide pinout. It supports hardware/software data protection and is used in industrial control firmware storage where low-voltage operation and reliable nonvolatile write endurance are required.
For engineers reviewing the AT28LV256-25SI datasheet, AT28LV256-25SI pinout, AT28LV256-25SI application, or AT28LV256-25SI equivalent, key selection criteria include industrial temperature range (-40°C to +85°C), 10,000 write/erase cycles, DATA polling and toggle-bit write completion detection, 64-byte page write capability, and compatibility with standard SRAM-like bus interfaces without external timing logic.
Technical Context
The AT28LV256-25SI implements a parallel EEPROM architecture with internal 64-byte page latches and an autonomous control timer for self-timed write operations. Its read interface mirrors static RAM behavior: CE and OE low with WE high enables true data output, while CE or OE high places I/O pins in high-impedance state.
Write operations support both byte and page modes. Page writes require all addresses to reside within the same 64-byte boundary (A6–A14 fixed), with successive bytes loaded within 150 µs (tBLC); software data protection mandates a three-command unlock sequence before any write, and device identification uses dedicated 64-byte memory space accessible via A9 = 12V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 256 Kbit (32,768 × 8 bits) - supports full firmware image or configuration table storage in legacy 8-bit microcontroller systems |
| Read Access Time | 250 ns - ensures compatibility with 4 MHz Z80, 8051, and similar legacy bus timing without wait states |
| Page Write Cycle Time | 10 ms max - enables efficient bulk parameter updates without host CPU blocking for extended durations |
| Supply Voltage | 3.0 V – 3.6 V - operates directly from modern low-voltage logic rails, eliminating level-shifting in 3.3 V systems |
| Endurance | 10,000 write/erase cycles - sufficient for field-upgradable calibration data or infrequent configuration changes over product lifetime |
| Data Retention | 10 years at 85°C - guarantees long-term validity of stored settings in industrial environments without battery backup |
| Standby Current | 20 µA (CMOS, commercial temp) / 50 µA (industrial temp) - minimizes power draw in always-on embedded controllers during sleep modes |
Pinout & Package
AT28LV256-25SI is packaged in a 28-lead SOIC (28S) with JEDEC-standard byte-wide pinout. Pin functions are electrically identical across PDIP, SOIC, TSOP, and PLCC variants per datasheet Rev. 2400AX.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define 64-byte page boundaries for page write mode |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path; supports DATA polling on I/O7 and toggle-bit detection on I/O6 during write cycles |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read access; inhibits writes when high |
| OE | Output Enable | Active-low output control; enables data output only when CE is also low; high-Z when deasserted |
| WE | Write Enable | Active-low write strobe; initiates byte or page write on falling edge; combined with CE for dual-control write safety |
| VCC | Power Supply | 3.0–3.6 V supply input; includes internal VCC power-on delay (~10 ms) to prevent inadvertent writes during power ramp |
| GND | Ground Reference | Signal and power ground reference for all I/O and internal circuitry |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Requires three specific unlock commands (5555H/55H, 2AAAH/AAH, 5555H/A0H) before each write - prevents corruption during power transitions or noise events |
| Hardware Write Inhibit | Automatic 10 ms VCC power-on delay plus OE/CE/WE logic-level inhibition - eliminates need for external reset sequencing circuitry |
| 64-Byte Page Write | Internal latching allows up to 64 bytes to be loaded and written in one self-timed operation - reduces host CPU overhead by >90% vs. byte-by-byte writes |
| DATA Polling & Toggle Bit | I/O7 complement output and I/O6 toggling provide real-time, bus-compatible write completion signaling - no external status lines or timers needed |
| Device Identification Area | Dedicated 64-byte EEPROM region (7FC0H–7FFFH) accessible with A9 = 12V - enables unique serialization, calibration storage, or revision tracking |
Applications
| Industrial PLC Configuration Storage | Legacy Microcontroller Firmware Backup |
|---|---|
Use Scenario: Storing user-configurable I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank with SRAM-compatible read interface and page-write efficiency for infrequent but critical updates. Use Value: Eliminates battery-backed SRAM; 10,000-cycle endurance exceeds typical field maintenance intervals; 20 µA standby current extends uptime in unpowered cabinets. |
Use Scenario: Holding boot code checksums, bootloader patches, and peripheral initialization tables for 8051- and Z80-based embedded instruments with no flash memory. IC Role / Device Role / Timing Role: Parallel memory replacement for obsolete EPROM sockets, leveraging identical JEDEC pinout and 250 ns timing. Use Value: Enables in-system reprogramming without UV erasers; 3.3 V operation avoids level shifters; software protection prevents accidental overwrite during debug sessions. |
| Medical Device Calibration Data | Telecom Line Card Parameter Tables |
Use Scenario: Storing sensor offset/gain coefficients and patient safety limits in portable diagnostic equipment requiring regulatory-compliant data persistence. IC Role / Device Role / Timing Role: Tamper-resistant calibration vault with dual hardware/software write lock and 10-year data retention at 85°C. Use Value: Meets IEC 62304 traceability requirements; 12V-programmable ID area stores manufacturing lot and calibration timestamp; industrial temp grade ensures reliability in sterilized enclosures. |
Use Scenario: Maintaining line impedance profiles, gain settings, and fault-history logs across multiple E1/T1 interface cards in carrier-grade DSLAMs. IC Role / Device Role / Timing Role: Shared configuration memory accessible by multiple ASICs via common bus; supports concurrent read while write-polling. Use Value: Page write reduces configuration update latency during service provisioning; DATA polling allows deterministic interrupt-driven status handling without polling overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-25PI | 5V-only supply (4.5–5.5 V); 250 ns access; same 256K × 8 organization and JEDEC pinout | Requires 5 V rail and level translation in 3.3 V systems; lacks low-voltage write optimization | Select when legacy 5 V infrastructure exists and voltage scaling is not required |
| ST M28W256FBD-25N6 | 3.3 V supply; 256K × 8; 250 ns access; integrated hardware write protect (WP# pin); no software unlock sequence | Hardware WP# simplifies design but removes fine-grained software control; different pinout (WP# replaces NC) | Select when board layout allows pinout change and deterministic hardware lockout is preferred over flexible SDP |
Compared with AT28LV256-25SI, AT28C256-25PI requires higher voltage and lacks low-power write features, while ST M28W256FBD-25N6 offers simpler hardware protection but sacrifices pin compatibility and software-controlled flexibility-making AT28LV256-25SI optimal for drop-in 3.3 V upgrades of legacy designs.
Availability
AT28LV256-25SI is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, telecom line cards, and legacy microcontroller firmware storage requiring stable component supply across extended product lifecycles.
Supply support for AT28LV256-25SI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial, automotive, and consumer applications.
The AT28LV256 product line delivers low-voltage, high-reliability parallel EEPROMs designed for firmware backup, configuration storage, and calibration data retention in systems where SRAM+backup-battery or flash memory are impractical.
FAQ
What is the operating temperature range for the AT28LV256-25SI?
The AT28LV256-25SI is rated for industrial temperature operation from -40°C to +85°C. This specification is confirmed in the "DC and AC Operating Range" table on page 4 of the official datasheet (Rev. 2400AX), where the "-25SI" suffix explicitly denotes the industrial-grade SOIC variant. The device maintains full functionality-including 250 ns read access, 10 ms page write, and 20 µA standby current-across this entire range.
Does the AT28LV256-25SI require a 12V programming voltage?
The AT28LV256-25SI operates from 3.0–3.6 V for normal read/write functions, but a 12.0 V ± 0.5 V supply on pin A9 is required only to access the dedicated 64-byte device identification area (7FC0H–7FFFH). Standard memory operations-including all page and byte writes using software data protection-use only the 3.3 V VCC rail. The 12 V requirement is isolated to optional serialization/calibration storage.
How does software data protection work on the AT28LV256-25SI?
Software data protection on the AT28LV256-25SI requires a precise three-command unlock sequence before any write: write 0x55 to address 0x5555, then 0xAA to address 0x2AAA, then 0xA0 to address 0x5555. Only after this sequence is completed can byte or page writes proceed. If omitted, the device enters polling mode for tWC (10 ms) but writes no data-ensuring robust immunity to spurious signals during power transitions.
Can the AT28LV256-25SI be used as a direct replacement for the AT28C256?
No-the AT28LV256-25SI is not a direct replacement for the AT28C256 due to fundamental supply voltage differences: AT28C256 requires 4.5–5.5 V, while AT28LV256-25SI operates at 3.0–3.6 V. Although both share JEDEC byte-wide pinouts and 256K × 8 organization, mixing them risks under-voltage operation or damage. A level-shifting interface or board redesign is required for substitution.
What package type is used for the AT28LV256-25SI?
The AT28LV256-25SI uses a 28-lead, 0.300" wide plastic gull-wing small outline integrated circuit (SOIC) package, designated as "28S" in Atmel's ordering information (page 10 of datasheet Rev. 2400AX). This surface-mount package has standard JEDEC MS-012AB dimensions and is compatible with automated PCB assembly processes.
AT28LV256-25SI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28LV256-25SI FAQ
1.How can I place an order for AT28LV256-25SI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV256-25SI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV256-25SI reliable?
The price and inventory of AT28LV256-25SI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV256-25SI is usually 5 days.
3.What payment methods are accepted for AT28LV256-25SI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV256-25SI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV256-25SI?
AT28LV256-25SI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV256-25SI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV256-25SI?
For technical support, including AT28LV256-25SI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV256-25SI requirements.
6.How does Aetrix verify that AT28LV256-25SI is sourced from the original manufacturer or authorized distributors?
All AT28LV256-25SI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV256-25SI meets industry standards.
7.What is the process for return or replacement of AT28LV256-25SI?
All AT28LV256-25SI units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV256-25SI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV256-25SI part is unused and in its original packaging.
Return procedure for AT28LV256-25SI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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