Microchip Technology AT28LV256-25TC
- Part No.:
- AT28LV256-25TC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-TSSOP (0.465", 11.80mm Width)
- Datasheet:
-
AT28LV256-25TC.pdf
- Description:
- IC EEPROM 256KBIT PAR 28TSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,666
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28LV256-25TC from Atmel is a 256 Kbit (32K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 3.0–3.6 V single-supply operation, 250 ns read access time, and hardware/software data protection. It supports page write (1–64 bytes), DATA polling, and Toggle Bit for write completion detection - used in industrial control firmware storage and embedded boot memory.
For engineers reviewing the AT28LV256-25TC datasheet, AT28LV256-25TC pinout, AT28LV256-25TC application, or AT28LV256-25TC equivalent, key selection criteria include low-voltage compatibility, page-write timing (≤10 ms), CMOS standby current (≤20 µA), endurance (10,000 cycles), and JEDEC-compliant 28-pin TSOP packaging.
Technical Context
The AT28LV256-25TC operates as a drop-in SRAM-compatible nonvolatile memory: CE/OE/WE control enables standard bus interfacing without external logic. Its internal 64-byte page register latches address and data on falling CE or WE edges, decoupling the host bus during autonomous internal programming.
Write completion is verified via I/O7 DATA polling (complement-to-data toggle) or I/O6 Toggle Bit behavior, both functional across all operating modes. Hardware protection includes VCC power-on delay (~10 ms), noise filtering (<15 ns pulse rejection), and active inhibit states (CE high, OE low, or WE high).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32,768 × 8 bits) - supports full firmware image storage for microcontrollers with 8-bit data buses. |
| Read Access Time | 250 ns max - compatible with 4 MHz system clocks and legacy ISA/PCI bus timing budgets. |
| Page Write Cycle | ≤10 ms - enables efficient bulk configuration updates without blocking host CPU for extended periods. |
| VCC Supply Range | 3.0 V to 3.6 V - interoperable with 3.3 V logic families and eliminates need for level shifters. |
| Standby Current | 20 µA (CMOS) - suitable for battery-backed systems requiring ultra-low quiescent power. |
| Endurance | 10,000 write/erase cycles - sufficient for field-upgradable calibration tables and parameter logging. |
| Data Retention | 10 years at 85°C - meets industrial temperature lifecycle requirements for unattended equipment. |
Pinout & Package
AT28LV256-25TC uses a 28-lead Plastic Thin Small Outline Package (TSOP), 8 mm × 13.4 mm body, 0.55 mm pitch, JEDEC MO-153 compliant. Pin 1 index marked, lead finish SnPb or RoHS-compliant matte tin.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte writes. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; I/O7 provides DATA polling status, I/O6 delivers Toggle Bit confirmation. |
| CE | Chip Enable | Active-low chip select; must be stable before address setup; inhibits writes when high. |
| OE | Output Enable | Active-low output control; enables read data drive; high-Z when deasserted to prevent bus contention. |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; combined with CE for robust write initiation. |
| VCC | Power Supply | 3.0–3.6 V supply; internal voltage monitor enforces 10 ms power-on write inhibit delay. |
| GND | Ground Reference | Signal and power return; decoupling capacitor required within 10 mm of VCC pin. |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Three-step unlock sequence (5555H/2AAAH/5555H) required before each write - prevents corruption during power transients. |
| Hardware Write Inhibit | Automatic 10 ms VCC power-on delay + noise-filtered CE/WE inputs - eliminates false writes from supply bounce or EMI. |
| Page Write Architecture | Internal 64-byte latch allows burst loading of up to 64 bytes within 150 µs intervals - reduces host bus occupancy by >90% vs. byte writes. |
| JEDEC Byte-Wide Pinout | Pin-compatible with industry-standard EPROMs and SRAMs (e.g., 27C256, 62256) - enables direct replacement in existing PCB layouts. |
| Device Identification Area | 64-byte reserved sector (7FC0H–7FFFH) accessible via 12 V on A9 - supports unique device serialization and traceability. |
Applications
| Industrial PLC Firmware Storage | Medical Device Calibration Memory |
|---|---|
|
Use Scenario: Storing firmware update images and configuration parameters in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile program memory with SRAM-like read interface and page-write efficiency for field upgrades. Use Value: 250 ns read speed ensures real-time instruction fetch; 10,000-cycle endurance supports quarterly firmware revisions over 10+ year product life. |
Use Scenario: Retaining calibrated sensor offsets and safety-critical operational limits in portable diagnostic equipment operating across -40°C to +85°C. IC Role / Device Role / Timing Role: Temperature-stable configuration storage with hardware write protection against accidental reprogramming during battery swaps. Use Value: 20 µA standby current extends battery life; industrial temp range (-40°C to +85°C) and 10-year data retention meet IEC 62304 Class C requirements. |
| Telecom Line Card Boot Memory | Automotive Body Control Module NVM |
|
Use Scenario: Holding bootloader code and initialization tables for FPGA-based line cards in carrier-grade DSLAMs and OLTs. IC Role / Device Role / Timing Role: Parallel boot ROM accessed directly by microprocessor address/data bus during power-on reset sequence. Use Value: JEDEC pinout enables drop-in replacement of obsolete EPROMs; 3.3 V compatibility avoids level-shifter redesign. |
Use Scenario: Storing vehicle-specific configuration (e.g., door lock logic, mirror position presets) in BCMs subject to automotive thermal cycling. IC Role / Device Role / Timing Role: Robust parameter memory with dual hardware/software write protection to prevent corruption during ignition transients. Use Value: 12 V A9 programming mode enables secure device ID writing during manufacturing; 10,000-cycle rating exceeds OEM 15-year service life targets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W256FCT | 256 Kbit, 3.3 V, 200 ns access, but requires 5 V for write operations and lacks software data protection. | Not suitable for fully 3.3 V-only systems; higher VPP complexity increases BOM count and layout area. | Select only if legacy 5 V programming infrastructure exists and SDP is not required. |
| Microchip 25LC256-I/P | 256 Kbit SPI EEPROM, 3.3 V, 5 ms page write, no parallel bus interface - serial protocol only. | Requires MCU SPI peripheral and firmware driver; incompatible with SRAM-style bus-mapped access. | Choose only for new designs where board space is constrained and SPI is already utilized for other peripherals. |
Compared with ST M28W256FCT and Microchip 25LC256-I/P, the AT28LV256-25TC uniquely delivers true 3.3 V-only operation with JEDEC-compliant parallel interface, integrated SDP, and deterministic 10 ms page write - enabling direct replacement in legacy SRAM/EPROM sockets without redesign.
Availability
AT28LV256-25TC is available at Aetrix Electronics and suitable for industrial control firmware storage, medical device calibration memory, and telecom line card boot memory requiring stable component supply, long-term lifecycle support, and RoHS-compliant TSOP packaging.
Supply support for AT28LV256-25TC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and security ICs for industrial, automotive, and communications markets.
The AT28LV256-25TC belongs to Atmel's Low-Voltage™ Parallel EEPROM product line, designed specifically for 3.3 V embedded systems needing SRAM-compatible nonvolatile storage with robust write protection and industrial temperature operation.
FAQ
What is the maximum read access time specified for the AT28LV256-25TC?
The AT28LV256-25TC has a maximum read access time of 250 ns under commercial temperature conditions (0°C to 70°C) and 3.0–3.6 V supply. This value is guaranteed across the full operating voltage and temperature range, ensuring reliable timing integration into 4 MHz bus systems without wait-state insertion. The AT28LV256-25TC achieves this using optimized CMOS decoding and output drivers, consistent with its JEDEC byte-wide pinout compatibility.
Does the AT28LV256-25TC support page write operations, and what is the maximum page size?
Yes, the AT28LV256-25TC supports page write operations with a fixed 64-byte page size. Up to 64 bytes can be loaded sequentially within 150 µs intervals, after which the internal timer initiates autonomous programming. The AT28LV256-25TC uses A6–A14 to define the page boundary, and all addresses in a given page write must share identical A6–A14 values - enabling efficient firmware patching without repeated address setup overhead.
How does hardware write protection work on the AT28LV256-25TC?
The AT28LV256-25TC implements three hardware write protection mechanisms: (1) a 10 ms VCC power-on delay that blocks writes until supply stabilizes; (2) active inhibition when CE is high, OE is low, or WE is high; and (3) input noise filtering rejecting pulses <15 ns on CE/WE. These features ensure the AT28LV256-25TC remains immune to spurious writes during power sequencing, ESD events, or signal crosstalk - critical for unattended industrial deployments.
Can the AT28LV256-25TC be used in industrial temperature applications?
Yes, the AT28LV256-25TC is qualified for industrial temperature operation from -40°C to +85°C, as confirmed by its ordering code suffix "TI" (industrial) and "TC" (TSOP package). Its 10-year data retention and 10,000-cycle endurance are validated across this full range. The AT28LV256-25TC maintains 250 ns read access and ≤10 ms page write performance throughout the industrial temperature envelope, making it suitable for harsh-environment control systems.
What is the purpose of the extra 64-byte EEPROM section in the AT28LV256-25TC?
The AT28LV256-25TC includes an additional 64-byte EEPROM segment (addresses 7FC0H–7FFFH) accessible only when A9 is raised to 12.0 V ± 0.5 V. This area is intended for permanent device identification, manufacturing traceability, or secure key storage - isolated from normal read/write operations. Unlike main array accesses, this region requires elevated voltage and dedicated programming sequences, ensuring the AT28LV256-25TC supports secure provisioning without compromising main memory reliability.
AT28LV256-25TC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.465", 11.80mm Width)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSOP
AT28LV256-25TC FAQ
1.How can I place an order for AT28LV256-25TC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV256-25TC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV256-25TC reliable?
The price and inventory of AT28LV256-25TC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV256-25TC is usually 5 days.
3.What payment methods are accepted for AT28LV256-25TC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV256-25TC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV256-25TC?
AT28LV256-25TC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV256-25TC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV256-25TC?
For technical support, including AT28LV256-25TC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV256-25TC requirements.
6.How does Aetrix verify that AT28LV256-25TC is sourced from the original manufacturer or authorized distributors?
All AT28LV256-25TC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV256-25TC meets industry standards.
7.What is the process for return or replacement of AT28LV256-25TC?
All AT28LV256-25TC units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV256-25TC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV256-25TC part is unused and in its original packaging.
Return procedure for AT28LV256-25TC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28LV256-25TC Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

