Microchip Technology AT28LV64B-20JI
- Part No.:
- AT28LV64B-20JI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28LV64B-20JI.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28LV64B-20JI from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with 3.3 V ±10% single-supply operation, 200 ns read access time, and hardware/software data protection. It supports page write (1–64 bytes), DATA polling, and toggle-bit write completion detection, and is rated for industrial temperature (−40°C to +85°C) in 32-lead PLCC package.
For engineers reviewing the AT28LV64B-20JI datasheet, AT28LV64B-20JI pinout, AT28LV64B-20JI application, or AT28LV64B-20JI equivalent, this device serves as a drop-in replacement for legacy 5 V EEPROMs in space-constrained industrial control, embedded instrumentation, and firmware storage where low-voltage operation and write-cycle reliability are critical.
Technical Context
The AT28LV64B-20JI implements a CMOS-based parallel EEPROM architecture with JEDEC-standard byte-wide pinout and internal 64-byte page register. Its dual-line chip enable (CE) and output enable (OE) control enables bus contention avoidance in multi-device systems.
Write operations require a three-byte software data protection (SDP) sequence before each byte or page write; hardware protection includes VCC power-on delay (~10 ms), noise filtering (<15 ns pulse rejection), and CE/OE/WE state-dependent write inhibit. Device identification uses dedicated 64-byte memory block accessible via A9 = 12 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable nonvolatile storage |
| Supply Voltage | 3.3 V ±10% - eliminates level-shifting in modern 3.3 V microcontroller interfaces |
| Read Access Time | 200 ns - compatible with 5 MHz bus timing without wait states |
| Page Write Cycle | ≤10 ms - enables efficient firmware patching with up to 64-byte atomic writes |
| Endurance | 100,000 write/erase cycles - supports field-upgradable embedded applications over product lifetime |
| Data Retention | 10 years at 85°C - validated for long-term deployment in industrial environments |
| Standby Current | 20 µA (CMOS) - enables ultra-low-power sleep modes in battery-backed systems |
Pinout & Package
AT28LV64B-20JI is packaged in a 32-lead Plastic J-Leaded Chip Carrier (PLCC), pin-compatible with JEDEC MS-016AE standard. Pin 1 is index-marked; pins 1 and 17 are designated "Don't Connect" (DC) per datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus for full 8K-word addressing; A6–A12 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional Data Bus | Byte-wide parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit status indication |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; write inhibited if high |
| OE | Output Enable | Active-low output control; high-Z when high, enabling shared bus operation |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; must follow SDP command sequence |
| VCC | Power Supply | 3.3 V ±10% supply; internal power-on delay prevents spurious writes during ramp-up |
| GND | Ground Reference | Signal and power return; decoupling capacitor required within 1 cm of VCC/GND pins |
| NC / DC | No Connect / Don't Connect | Pins 1 and 17 are unconnected; must remain floating - no PCB trace or solder mask opening |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Three-byte unlock sequence (AAh→55h→A0h) required before every write - prevents corruption during power transitions |
| Page Write Capability | Internal 64-byte latch allows burst programming without external address/data bus hold - reduces host CPU overhead by >90% vs. byte-by-byte writes |
| DATA Polling & Toggle Bit | Dual asynchronous write-completion detection on I/O7 (complement read) and I/O6 (toggle) - eliminates need for fixed delays or external timers |
| Industrial Temperature Range | −40°C to +85°C operation - qualified for use in motor drives, PLC modules, and outdoor telemetry equipment |
| Device Identification Memory | 64-byte reserved block (7FC0h–7FFFh) accessible at 12 V on A9 - enables unique serialization and calibration data storage |
Applications
| Industrial PLC Configuration Storage | Firmware Patch Storage in Medical Devices |
|---|---|
Use Scenario: Storing user-configurable I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via parallel bus during boot and runtime reconfiguration; 200 ns read latency ensures real-time parameter updates. Use Value: Enables field-upgradable settings without requiring full firmware reload; 100,000-cycle endurance supports decades of maintenance cycles in unattended installations. |
Use Scenario: Holding safety-critical firmware patches that must be applied post-deployment in Class II medical infusion pumps. IC Role / Device Role / Timing Role: Secure, low-voltage EEPROM storing signed update payloads; SDP and hardware write inhibit prevent accidental overwrite during brownout conditions. Use Value: Guarantees integrity of life-supporting code updates; 10-year data retention meets FDA 21 CFR Part 11 archival requirements for electronic records. |
| Embedded Instrumentation Calibration Data | Telecom Line Card Bootloader Parameters |
Use Scenario: Storing factory-calibrated ADC offset/gain coefficients and sensor linearization tables in portable multimeters and oscilloscopes. IC Role / Device Role / Timing Role: Byte-addressable nonvolatile memory mapped into microcontroller address space; accessed only during self-test or calibration mode. Use Value: Eliminates need for external calibration potentiometers; 64-byte page write allows atomic update of full calibration set without partial-write corruption. |
Use Scenario: Holding boot configuration flags, MAC address, and FPGA bitstream checksums on carrier-grade DSLAM line cards operating in telecom central offices. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to ARM9 boot ROM controller; read during cold start prior to DDR initialization. Use Value: Ensures deterministic boot behavior across temperature extremes; 20 µA standby current minimizes board-level leakage in always-on infrastructure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Microchip 25LC640-I/P | Serial SPI interface (not parallel); 5 V tolerant; 5 ms max write cycle; no SDP sequence | Requires SPI controller and software driver; unsuitable for direct bus-mapped read/write | Select only if board layout supports serial interface and MCU lacks parallel bus or has limited GPIO |
| ON Semiconductor CAT28LV64A-20JI | Pin-compatible PLCC variant; identical 3.3 V, 200 ns, 64K×8 spec; same SDP sequence and page write timing | Drop-in replacement with identical footprint, timing, and software interface; qualified to same industrial temp range | Preferred for second-source assurance where Atmel supply continuity is constrained |
Compared with Microchip 25LC640-I/P, AT28LV64B-20JI delivers deterministic parallel access and hardware write safety but requires more PCB area; versus CAT28LV64A-20JI, it offers identical functionality with proven field reliability in legacy industrial designs.
Availability
AT28LV64B-20JI is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, and telecom infrastructure requiring stable component supply, long-lifecycle support, and guaranteed industrial-temperature qualification.
Supply support for AT28LV64B-20JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT28LV64B product line was designed for embedded systems requiring reliable, low-voltage parallel EEPROM with robust data integrity features - targeting industrial, medical, and communications equipment where firmware and configuration persistence is mission-critical.
FAQ
What is the operating voltage range for AT28LV64B-20JI?
The AT28LV64B-20JI operates from a single 3.3 V supply with ±10% tolerance (2.97 V to 3.63 V). This eliminates the need for dual 5 V/3.3 V rails in mixed-signal systems and ensures compatibility with modern low-voltage microcontrollers. The device incorporates internal power-on delay circuitry that prevents write operations until VCC stabilizes above 1.8 V, making AT28LV64B-20JI inherently resistant to power-rail glitches during startup or brownout conditions.
Does AT28LV64B-20JI support true parallel byte writes without external timing logic?
Yes, AT28LV64B-20JI supports fully autonomous byte and page writes after the initial software data protection (SDP) unlock sequence. Once the three-byte SDP command (AAh→55h→A0h) is issued, the device internally latches address and data, manages the 10 ms write cycle using its internal control timer, and signals completion via DATA polling on I/O7 or toggle-bit behavior on I/O6 - no external wait-state generator or timing circuitry is required for AT28LV64B-20JI integration.
How does the software data protection (SDP) mechanism work in AT28LV64B-20JI?
The AT28LV64B-20JI requires a precise three-byte unlock sequence written to specific addresses (1555h→0AAAh→1555h) with defined data values (AAh→55h→A0h) before any write operation. This SDP sequence must be repeated before every byte or page write. If omitted, AT28LV64B-20JI enters a polling state where reads return invalid data for the duration of tWC (10 ms), preventing silent corruption - a critical safeguard during power transitions or firmware bugs.
Can AT28LV64B-20JI be used as a direct replacement for older 5 V EEPROMs like AT28C64B?
No, AT28LV64B-20JI is not a direct replacement for 5 V devices such as AT28C64B due to its 3.3 V-only supply requirement and incompatible input voltage thresholds (VIH = 2.0 V, VIL = 0.6 V). Interfacing with 5 V systems requires level translation on all control and data lines. However, AT28LV64B-20JI shares identical JEDEC byte-wide pinout and instruction set with AT28C64B, so software drivers and PCB layout can be reused with appropriate voltage adaptation for AT28LV64B-20JI.
What is the purpose of the 64-byte device identification memory in AT28LV64B-20JI?
The AT28LV64B-20JI includes a dedicated 64-byte memory block (addresses 7FC0h–7FFFh) accessible only when A9 is raised to 12.0 V ±0.5 V. This area is intended for permanent device-specific data such as factory calibration constants, serial numbers, or manufacturing lot codes. Unlike main array writes, this region does not require the SDP sequence, but its use mandates a high-voltage programming circuit - a feature leveraged in precision test equipment and regulated medical devices for traceability and compliance reporting.
AT28LV64B-20JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28LV64B-20JI FAQ
1.How can I place an order for AT28LV64B-20JI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV64B-20JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV64B-20JI reliable?
The price and inventory of AT28LV64B-20JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV64B-20JI is usually 5 days.
3.What payment methods are accepted for AT28LV64B-20JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV64B-20JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV64B-20JI?
AT28LV64B-20JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV64B-20JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV64B-20JI?
For technical support, including AT28LV64B-20JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV64B-20JI requirements.
6.How does Aetrix verify that AT28LV64B-20JI is sourced from the original manufacturer or authorized distributors?
All AT28LV64B-20JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV64B-20JI meets industry standards.
7.What is the process for return or replacement of AT28LV64B-20JI?
All AT28LV64B-20JI units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV64B-20JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV64B-20JI part is unused and in its original packaging.
Return procedure for AT28LV64B-20JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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