My Inquiry
My Account
Microchip Technology AT28LV64B-20SC
- Part No.:
- AT28LV64B-20SC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28LV64B-20SC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,152
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28LV64B-20SC from Atmel is a 64 Kbit (8K × 8) low-voltage parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, 3.3 V ±10% supply operation, and hardware/software data protection. It supports page write (1–64 bytes), DATA polling, and toggle-bit write completion detection for embedded control and firmware storage applications.
For engineers reviewing the AT28LV64B-20SC datasheet, AT28LV64B-20SC pinout, AT28LV64B-20SC application, or AT28LV64B-20SC equivalent, key selection considerations include its 20 µA CMOS standby current, 10 ms maximum page write cycle, 100,000 write endurance, industrial temperature range (−40°C to +85°C), and SOIC-28 package compatibility with legacy 8-bit microcontroller buses.
Technical Context
The AT28LV64B-20SC operates as a drop-in parallel memory replacement for SRAM or EPROM in 8-bit systems, requiring no external timing logic. Its internal 64-byte page register latches address and data on falling CE/WE edges, enabling bus release during autonomous internal programming.
Write completion is verified via I/O7 DATA polling (complement-to-data transition) or I/O6 toggle-bit behavior-both usable at any point during tWC. Software Data Protection mandates a three-byte unlock sequence (0xAA→0x55→0xA0 at 0x1555/0x0AAA/0x1555) before each write, preventing corruption during power transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits); sufficient for boot code, calibration tables, or configuration storage in resource-constrained controllers |
| Read Access Time | 200 ns max; enables direct interface with 5 MHz bus systems without wait states |
| Page Write Cycle | 10 ms max; allows efficient bulk updates of up to 64 bytes per command, reducing host CPU overhead |
| Supply Voltage | 3.3 V ±10%; compatible with modern low-voltage logic families and eliminates need for level shifters |
| Standby Current | 20 µA (CMOS); critical for battery-backed or always-on embedded systems requiring ultra-low quiescent power |
| Endurance | 100,000 write cycles; supports frequent field-updatable parameters in industrial controllers and metering devices |
| Data Retention | 10 years at 85°C; ensures long-term reliability in automotive and industrial environments without refresh |
Pinout & Package
AT28LV64B-20SC is supplied in a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC) package per JEDEC MS-012AB, pin-compatible with industry-standard 28-pin parallel EEPROMs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; A6–A12 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit write status indication |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; initiates write when low with OE high and WE low |
| OE | Output Enable | Active-low output control; disables outputs (high-Z) when high, preventing bus contention during writes or standby |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; combined with CE and OE determines operation mode |
| VCC | Power Supply | +3.3 V ±10% supply; powers core logic and I/O; includes internal power-on delay (~10 ms) for hardware write inhibit |
| GND | Ground Reference | Signal and power ground reference; required for stable read/write margins and noise immunity |
| NC | No Connect | Unbonded pins (SOIC pins 1 and 28); must remain unconnected per datasheet to avoid functional disruption |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Three-byte unlock sequence (0xAA/0x55/0xA0) required before every write, eliminating risk of spurious writes during power ramp-up/down |
| Hardware Write Inhibit | Automatic 10 ms VCC power-on delay plus noise filtering (<15 ns pulses rejected) and dual-line control (CE/OE/WE logic) prevent accidental writes |
| Page Write Architecture | Internal 64-byte latch frees address/data bus after initial byte load, enabling concurrent host operations during 10 ms internal programming |
| DATA Polling & Toggle Bit | Dual asynchronous write-completion detection: I/O7 complement transition or I/O6 toggling-no timer or fixed delays needed in host firmware |
| Device Identification Area | Dedicated 64-byte user-accessible EEPROM block (7FC0H–7FFFH) enabled by 12 V on A9, supporting unique device serialization or calibration storage |
Applications
| Industrial PLC Configuration Storage | Automotive ECU Calibration Tables |
|---|---|
Use Scenario: Storing runtime-configurable I/O mapping, PID tuning parameters, and fault log history in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed via 8-bit parallel bus; 200 ns read latency meets real-time scan cycle deadlines. Use Value: 100,000 write cycles and 10-year data retention ensure reliable field updates over 15+ year product lifecycles without battery backup. |
Use Scenario: Holding sensor calibration coefficients, fuel trim values, and emission control thresholds updated during vehicle service or adaptive learning. IC Role / Device Role / Timing Role: Secure, low-power EEPROM interfaced to MCU's external memory bus; software data protection prevents corruption during ignition cycling. Use Value: 3.3 V operation eliminates level-shifting, while −40°C to +85°C rating guarantees functionality across engine bay thermal extremes. |
| Medical Device Firmware Bootloader | Point-of-Sale Terminal Security Keys |
Use Scenario: Storing signed bootloader images and secure boot configuration flags in Class II medical instruments requiring FDA audit trails. IC Role / Device Role / Timing Role: Trusted nonvolatile memory for verified firmware launch; page write enables atomic image updates with minimal downtime. Use Value: Hardware + software write protection meets IEC 62304 safety requirements for preventing unauthorized or corrupted firmware execution. |
Use Scenario: Securing cryptographic keys, transaction logs, and tamper-evident audit counters in PCI-DSS compliant payment terminals. IC Role / Device Role / Timing Role: Tamper-resistant configuration store with dedicated identification area (7FC0H–7FFFH) for device-specific key binding. Use Value: 20 µA standby current extends battery life in offline terminals, while 12 V A9 programming enables secure key injection during manufacturing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECT | 64 Mbit (8M × 8), 3.3 V, 120 ns access, but requires 5 V for write; no built-in SDP sequence | Higher density suited for firmware storage, not parameter/config use; lacks robust low-voltage write safety | Select only if higher capacity and faster read are prioritized over write safety and 3.3 V-only operation |
| Microchip 25LC640A-I/SN | 64 Kbit SPI EEPROM, 2.5–5.5 V, 5 ms write cycle, software write protect, but serial interface | Reduces pin count and PCB space vs. parallel bus; incompatible with existing 8-bit address/data bus designs | Choose for new designs where SPI simplifies routing and layout, not for drop-in replacement of AT28LV64B-20SC |
Compared with ST M28W640ECT and Microchip 25LC640A-I/SN, the AT28LV64B-20SC uniquely delivers JEDEC-standard parallel pinout, true 3.3 V-only operation with hardware/software write protection, and deterministic 200 ns read timing-making it the only viable option for legacy 8-bit controller upgrades requiring zero bus redesign.
Availability
AT28LV64B-20SC is available at Aetrix Electronics and suitable for industrial automation, automotive electronics, and medical instrumentation requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for AT28LV64B-20SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and security ICs for embedded systems.
The AT28LV64B belongs to Atmel's low-voltage parallel EEPROM product line, designed specifically for 3.3 V systems needing pin-compatible, high-reliability replacements for older 5 V EEPROMs and EPROMs in industrial and automotive control applications.
FAQ
What is the operating temperature range for the AT28LV64B-20SC?
The AT28LV64B-20SC is rated for industrial temperature operation from −40°C to +85°C. This specification is confirmed in the Ordering Information table (page 10) and DC Operating Range section (page 4) of the datasheet, making it suitable for deployment in harsh environments such as factory floors, vehicle engine compartments, and outdoor infrastructure equipment where thermal stability is critical. The AT28LV64B-20SC maintains full functionality-including 200 ns read access and 10 ms page write-across this entire range.
Does the AT28LV64B-20SC require a 5 V supply for any function?
No, the AT28LV64B-20SC operates exclusively from a single 3.3 V ±10% supply (VCC = 2.97 V to 3.63 V) for all read, write, and standby functions. Unlike some legacy EEPROMs, it does not require elevated voltage for programming. The only exception is the optional device identification area (7FC0H–7FFFH), which uses 12 V on pin A9-but this is strictly for factory programming and not required for standard operation. The AT28LV64B-20SC's 3.3 V-only architecture eliminates level shifters and simplifies power design.
How does software data protection work on the AT28LV64B-20SC?
Software Data Protection (SDP) on the AT28LV64B-20SC requires a precise three-byte unlock sequence before any write: first write 0xAA to address 0x1555, then 0x55 to 0x0AAA, then 0xA0 to 0x1555. Only after this sequence is completed will subsequent byte or page writes be accepted. If omitted, the AT28LV64B-20SC ignores the data but still consumes the full 10 ms write cycle time. This mechanism prevents corruption during power transients and is mandatory for every write operation to the AT28LV64B-20SC.
Can the AT28LV64B-20SC be used as a direct replacement for the AT28C64B?
No-the AT28LV64B-20SC is not a pin-compatible or functional drop-in replacement for the AT28C64B. While both are 64 Kbit parallel EEPROMs, the AT28C64B requires 5 V for reads and 12 V for writes, whereas the AT28LV64B-20SC operates at 3.3 V only. Their pinouts differ: AT28C64B uses PDIP-28 with VPP on pin 1, while AT28LV64B-20SC (SOIC-28) has NC on pins 1 and 28. Interfacing the AT28LV64B-20SC in an AT28C64B design would require voltage translation and PCB layout changes.
What package type is used for the AT28LV64B-20SC?
The AT28LV64B-20SC uses a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC) package, designated as "28S" in Atmel's ordering codes. Its dimensions conform to JEDEC standard MS-012AB, with 1.27 mm lead pitch and body width of 7.62 mm. This SOIC package is surface-mount compatible, RoHS-compliant, and mechanically distinct from the PDIP-28 (28P6) and TSOP-28 (28T) variants of the same device family. The AT28LV64B-20SC's SOIC footprint supports automated assembly and high-density PCB layouts.
AT28LV64B-20SC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28LV64B-20SC FAQ
1.How can I place an order for AT28LV64B-20SC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV64B-20SC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV64B-20SC reliable?
The price and inventory of AT28LV64B-20SC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV64B-20SC is usually 5 days.
3.What payment methods are accepted for AT28LV64B-20SC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV64B-20SC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV64B-20SC?
AT28LV64B-20SC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV64B-20SC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV64B-20SC?
For technical support, including AT28LV64B-20SC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV64B-20SC requirements.
6.How does Aetrix verify that AT28LV64B-20SC is sourced from the original manufacturer or authorized distributors?
All AT28LV64B-20SC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV64B-20SC meets industry standards.
7.What is the process for return or replacement of AT28LV64B-20SC?
All AT28LV64B-20SC units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV64B-20SC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV64B-20SC part is unused and in its original packaging.
Return procedure for AT28LV64B-20SC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28LV64B-20SC Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
