Microchip Technology AT28LV64B-25JI
- Part No.:
- AT28LV64B-25JI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28LV64B-25JI.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28LV64B-25JI from Atmel is a 64K-bit (8K × 8) parallel EEPROM with single 3.3V ±10% supply, 250 ns read access time, 10 ms maximum page write cycle time, and hardware/software data protection. It operates across -40°C to +85°C industrial temperature range and supports JEDEC-standard byte-wide pinout for drop-in compatibility in legacy memory interfaces.
For engineers reviewing the AT28LV64B-25JI datasheet, AT28LV64B-25JI pinout, AT28LV64B-25JI application, or AT28LV64B-25JI equivalent, key selection criteria include its low-power CMOS standby current (≤50 µA), 64-byte page write capability, DATA polling and toggle bit write completion detection, and 100,000 write endurance for embedded firmware storage and configuration retention.
Technical Context
The AT28LV64B-25JI functions as a nonvolatile memory replacement for battery-backed SRAM or EPROM in microcontroller-based systems. Its architecture integrates an internal 64-byte page register, automatic control timer, and dual-line chip enable/output enable logic to emulate static RAM timing without external support circuitry.
Write operations require a three-byte software data protection (SDP) sequence before each byte or page write, and all writes are internally latched and self-timed. The device supports both byte and page write modes, with strict address alignment constraints (A6–A12 fixed per page) and 100 µs inter-byte load timing (tBLC) during page programming.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable parallel EEPROM |
| Read Access Time | 250 ns max - enables direct interface with 4–5 MHz microcontrollers without wait states |
| Page Write Cycle | 10 ms max - allows up to 64 bytes to be programmed in one atomic operation |
| Supply Voltage | 3.3 V ±10% - compatible with modern low-voltage logic families and eliminates need for 5V rails |
| Standby Current | 50 µA max (industrial temp) - supports ultra-low-power sleep modes in battery-operated devices |
| Endurance | 100,000 write/erase cycles - suitable for frequent configuration updates in field-deployed equipment |
| Data Retention | 10 years at 85°C - ensures long-term reliability in industrial control and automotive under-hood applications |
Pinout & Package
AT28LV64B-25JI is packaged in a 32-lead Plastic J-Leaded Chip Carrier (PLCC), compliant with JEDEC MS-016 AE. Pin 1 is index-marked; pins 1 and 17 are designated "Don't Connect" (DC) and must remain unconnected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; A6–A12 define page boundaries for page write mode |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path; I/O7 used for DATA polling, I/O6 for toggle-bit write status detection |
| CE | Chip Enable | Active-low global enable; when high, places outputs in high-impedance state and inhibits all writes |
| OE | Output Enable | Active-low output gate; controls data assertion on I/O lines during read; must be high during write |
| WE | Write Enable | Active-low write strobe; falling edge latches address and initiates byte/page write after SDP sequence |
| VCC | Power Supply | +3.3 V ±10% main supply; includes internal power-on delay (~10 ms) to prevent inadvertent writes at power-up |
| GND | Ground Reference | Signal and power return; decoupling capacitor required within 1 cm of VCC/GND pins |
| NC / DC | No Connect / Don't Connect | Pins 1 and 17 are internally unused and must float - no PCB trace or solder connection permitted |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Three-byte command sequence (AAh/55h/A0h) required before every write - prevents corruption during power transitions |
| Page Write Mode | 64-byte internal latch enables burst programming without CPU bus occupation between bytes |
| DATA Polling & Toggle Bit | Hardware-supported write completion detection via I/O7 complement or I/O6 toggling - eliminates need for fixed delays or external timers |
| Industrial Temperature Range | -40°C to +85°C operation - qualified for use in motor drives, PLCs, and outdoor telecom infrastructure |
| Dedicated Device ID Area | 64 bytes at 7FC0H–7FFFH accessible with A9 = 12V - enables unique serialization and calibration data storage |
Applications
| Industrial PLC Configuration Storage | Embedded Firmware Bootloader Storage |
|---|---|
Use Scenario: Storing user-configurable I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed infrequently but requiring guaranteed data integrity over 10+ years. Use Value: 100,000 write cycles and 10-year data retention ensure field reprogramming without degradation across maintenance cycles. |
Use Scenario: Holding bootloader code and secure boot keys in microcontroller-based edge devices with OTA update capability. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to MCU address/data bus for fast read access during cold boot. Use Value: 250 ns read access and JEDEC-compatible pinout allow seamless integration without glue logic or timing adjustments. |
| Automotive Body Control Module (BCM) | Medical Device Calibration Memory |
Use Scenario: Retaining seat/mirror position presets, lighting profiles, and diagnostic fault logs in 12V automotive systems with local 3.3V regulation. IC Role / Device Role / Timing Role: Low-voltage EEPROM operating from regulated 3.3V rail with robust noise immunity against engine cranking transients. Use Value: Hardware write inhibit (OE low/CE high/WE high) and 15 ns noise filter prevent spurious writes during electrical disturbances. |
Use Scenario: Storing factory-calibrated sensor offsets, linearity coefficients, and regulatory compliance metadata in Class II medical instruments. IC Role / Device Role / Timing Role: Tamper-resistant nonvolatile memory with software/hardware protection to meet IEC 62304 data integrity requirements. Use Value: SDP sequence and dedicated 64-byte ID area support secure device authentication and audit-trail-capable calibration logging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-25JI | 5V-only supply (4.5–5.5V); no low-voltage operation; identical 64K×8 organization and PLCC-32 package | Requires 5V system rail; lacks 3.3V compatibility and associated power savings | Select only if legacy 5V design prohibits voltage translation or regulator redesign |
| ST M28W640ECT-25N6 | 3.3V supply; 64Mbit (8M×8) density; 25 ns access; different pinout (SOIC-32); no SDP or page write | Higher density but incompatible interface; requires PCB redesign and firmware driver changes | Consider only for new designs needing >64K capacity and faster access, with full layout revision |
Compared with AT28LV64B-25JI, AT28C64B-25JI offers identical functionality at 5V but forfeits low-power advantage, while ST M28W640ECT-25N6 provides higher speed and density but demands complete hardware and software requalification.
Availability
AT28LV64B-25JI is available at Aetrix Electronics and suitable for industrial automation, automotive electronics, and medical device manufacturing requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for AT28LV64B-25JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT28LV64B product line was designed for reliable, low-voltage parallel EEPROM replacement in space-constrained industrial and automotive systems where battery backup is impractical and write endurance matters.
FAQ
What is the operating temperature range for AT28LV64B-25JI?
The AT28LV64B-25JI is rated for industrial temperature operation from -40°C to +85°C. This specification is confirmed in the Ordering Information table and DC Operating Range section of the datasheet, and applies to all electrical characteristics including read access time (250 ns max), standby current (≤50 µA), and write cycle timing. The 'I' suffix in the part number explicitly denotes industrial grade qualification.
Does AT28LV64B-25JI support true 3.3V-only operation without 5V or 12V auxiliary supplies?
Yes, AT28LV64B-25JI operates exclusively from a single 3.3V ±10% supply (2.97V to 3.63V) for all read, write, and standby functions. The 12V requirement mentioned in the datasheet applies only to the optional device identification area (7FC0H–7FFFH) and is not needed for standard memory operation. All core functionality - including SDP, page write, and DATA polling - works within the 3.3V domain.
How does software data protection (SDP) work on AT28LV64B-25JI?
AT28LV64B-25JI requires a mandatory three-byte SDP sequence (AAh to address 1555h, 55h to address 0AAAh, then A0h to address 1555h) before every byte or page write. This sequence arms the write logic; subsequent data writes to any address will only execute if preceded by this exact pattern. The SDP mechanism prevents accidental writes during power-up/down or EMI events, and is fully implemented in silicon - no external components or firmware overhead beyond the initial command burst.
Can AT28LV64B-25JI be used as a direct replacement for AT28C64B in existing designs?
No, AT28LV64B-25JI is not a direct replacement for AT28C64B due to fundamental supply voltage differences: AT28C64B requires 5V (4.5–5.5V), while AT28LV64B-25JI operates at 3.3V only. Although both share JEDEC byte-wide pinouts and 64K×8 organization, mixing voltages risks damage or undefined behavior. A level-shifting interface or system-level voltage redesign is required to migrate from AT28C64B to AT28LV64B-25JI.
What package type is used for AT28LV64B-25JI, and are all pins functional?
AT28LV64B-25JI uses a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package per JEDEC MS-016 AE. Pins 1 and 17 are explicitly marked "Don't Connect" (DC) in the datasheet and must remain unconnected on the PCB - they serve no internal function and connecting them violates the device's absolute maximum ratings. All other pins (A0–A12, I/O0–I/O7, CE, OE, WE, VCC, GND) are fully functional and electrically defined.
AT28LV64B-25JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28LV64B-25JI FAQ
1.How can I place an order for AT28LV64B-25JI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV64B-25JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV64B-25JI reliable?
The price and inventory of AT28LV64B-25JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV64B-25JI is usually 5 days.
3.What payment methods are accepted for AT28LV64B-25JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV64B-25JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV64B-25JI?
AT28LV64B-25JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV64B-25JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV64B-25JI?
For technical support, including AT28LV64B-25JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV64B-25JI requirements.
6.How does Aetrix verify that AT28LV64B-25JI is sourced from the original manufacturer or authorized distributors?
All AT28LV64B-25JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV64B-25JI meets industry standards.
7.What is the process for return or replacement of AT28LV64B-25JI?
All AT28LV64B-25JI units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV64B-25JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV64B-25JI part is unused and in its original packaging.
Return procedure for AT28LV64B-25JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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