Microchip Technology AT28LV64B-25PC
- Part No.:
- AT28LV64B-25PC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
AT28LV64B-25PC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28LV64B-25PC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with single 3.3 V ±10% supply, 250 ns read access time, 10 ms maximum page write cycle time, and JEDEC-standard byte-wide pinout. It operates across commercial temperature range (0°C to 70°C), supports hardware/software data protection, and delivers 15 mA active current and 20 µA CMOS standby current for low-power embedded nonvolatile storage.
For engineers reviewing the AT28LV64B-25PC datasheet, AT28LV64B-25PC pinout, AT28LV64B-25PC application, or AT28LV64B-25PC equivalent, key selection criteria include page-write capability (1–64 bytes), DATA polling/Toggle Bit end-of-write detection, software data protection command sequence, 100,000 write endurance, and compatibility with standard SRAM-like bus interfaces in microcontroller-based systems.
Technical Context
The AT28LV64B-25PC implements a static RAM-compatible parallel interface with dual-line chip enable (CE) and output enable (OE) control to prevent bus contention. Its internal 64-byte page register latches address and data during page writes, decoupling the host bus after initiation.
Write operations require a three-byte software data protection (SDP) sequence before any byte or page write; hardware protection includes VCC power-on delay (~10 ms), noise filtering (<15 ns pulse rejection), and write inhibit via CE/OE/WE logic states. End-of-write is confirmed via I/O7 DATA polling or I/O6 toggle bit behavior.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits) - provides sufficient nonvolatile storage for firmware patches, calibration data, or configuration registers in resource-constrained systems. |
| Read Access Time | 250 ns - enables direct replacement of fast SRAM in boot code or lookup table applications without wait-state insertion. |
| Page Write Cycle | ≤10 ms - allows efficient bulk updates of up to 64 bytes per operation, reducing host CPU overhead versus byte-by-byte programming. |
| Endurance | 100,000 write cycles - supports long-term field deployment in industrial logging or parameter tuning applications. |
| Data Retention | 10 years at 25°C - ensures reliable data persistence across product lifecycle without refresh circuitry. |
| Supply Voltage | 3.3 V ±10% - compatible with modern low-voltage microcontrollers and eliminates need for level-shifting in 3.3 V systems. |
| Standby Current | 20 µA (CMOS) - minimizes quiescent power in battery-backed or energy-harvesting designs. |
Pinout & Package
AT28LV64B-25PC is packaged in a 28-pin, 0.600" wide plastic dual in-line package (PDIP), compliant with JEDEC MS-016 AE standard. Pin 1 is index-marked; pins 1 and 28 are NC (no connect) in PDIP configuration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte page writes. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface supporting SRAM-style read/write; I/O7 used for DATA polling, I/O6 for Toggle Bit status indication. |
| CE | Chip Enable | Active-low global enable; when high, device enters high-impedance standby mode regardless of OE/WE state. |
| OE | Output Enable | Active-low control for output drivers; used with CE to manage bus contention during reads and polling. |
| WE | Write Enable | Active-low signal initiating byte or page write; must follow SDP command sequence to enable actual programming. |
| VCC | Power Supply | +3.3 V ±10% main supply; internal power-on delay prevents writes until stable voltage is reached. |
| GND | Ground Reference | Signal and power return path; required for proper logic threshold referencing and noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Three-byte command sequence (AAh→55h→A0h) required before every write; prevents corruption during power transitions or noise events. |
| Page Write Architecture | Internal 64-byte latch accepts 1–64 bytes within 100 µs intervals; frees host bus early and reduces total programming time by >90% vs. byte writes. |
| End-of-Write Detection | Dual methods: I/O7 complements last written byte until completion (DATA polling), or I/O6 toggles until write finishes (Toggle Bit). |
| JEDEC Byte-Wide Pinout | Pin-compatible with industry-standard EPROM/EEPROM families; simplifies PCB reuse and migration from legacy 27C64 or 28C64 devices. |
| Industrial-Grade Reliability | 100,000 write cycles and 10-year data retention validated per JEDEC JESD22-A117; suitable for unattended field equipment. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing user-configurable I/O mapping, alarm thresholds, and operational modes in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via parallel bus during system boot and runtime reconfiguration. Use Value: Enables field-upgradable settings without firmware reflashing; 250 ns read speed ensures zero-latency access during real-time scan cycles. |
Use Scenario: Retaining sensor calibration coefficients, patient history flags, and safety-critical operational limits in portable diagnostic instruments. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter vault with hardware/software write protection preventing accidental overwrites during power cycling. Use Value: Meets IEC 62304 Class B software requirements via 100,000-cycle endurance and 10-year data retention under medical-grade thermal profiles. |
| Automotive Body Control Module | Networking Equipment Bootloader Parameters |
Use Scenario: Holding door lock logic states, mirror position presets, and lighting profiles in automotive body control units operating across -40°C to +85°C. IC Role / Device Role / Timing Role: Temperature-stable nonvolatile memory interfaced directly to 8-bit MCU parallel bus; supports industrial temp grade (-40°C to +85°C) variant. Use Value: Eliminates external voltage supervisors or RC delays-built-in VCC power-on delay and noise filtering ensure robustness against automotive load dump transients. |
Use Scenario: Storing MAC address, firmware version hash, and network stack parameters in Ethernet switches and wireless access points. IC Role / Device Role / Timing Role: Fast-access configuration store enabling deterministic boot sequence timing and secure parameter recovery after unexpected resets. Use Value: 250 ns read access avoids boot bottlenecks; page write capability allows atomic updates of multi-field configuration blocks without partial-write risk. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-15PC | 5V-only supply (4.5–5.5 V); 150 ns access; no software data protection; 10,000 write cycles. | Lacks low-voltage operation and advanced write protection; suited only for legacy 5V systems with less stringent reliability needs. | Select only if existing 5V design forbids voltage translation and write endurance <10K cycles is acceptable. |
| M95640-DW DW | 3.3 V SPI interface; 5 MHz clock; 5 ms write time; 400 kHz I²C-compatible mode; no parallel bus. | Serial interface reduces pin count but increases software overhead; incompatible with SRAM-style bus timing and address/data multiplexing. | Choose for space-constrained designs where serial interface suffices and host MCU lacks parallel bus or has limited GPIO. |
Compared with AT28C64B-15PC, AT28LV64B-25PC enables 3.3 V system integration and superior data integrity via SDP; versus M95640-DW, it delivers deterministic parallel access and eliminates protocol stack dependencies-but requires more PCB real estate and dedicated address/data lines.
Availability
AT28LV64B-25PC is available at Aetrix Electronics and suitable for industrial PLC configuration storage, medical device calibration data retention, and automotive body control module applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for AT28LV64B-25PC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial, automotive, and consumer applications.
The AT28LV64B product line was designed as a drop-in upgrade path from 5V EPROM/EEPROMs, delivering low-voltage operation, enhanced write protection, and JEDEC-compliant pinouts for seamless integration into 3.3 V embedded systems.
FAQ
What is the maximum page write size supported by the AT28LV64B-25PC?
The AT28LV64B-25PC supports page write operations of 1 to 64 bytes per internal programming cycle. All bytes must reside on the same 64-byte page, defined by address bits A6–A12. The device internally latches addresses and data during the page load phase, enabling the host to release the bus after initial setup-this capability is explicitly confirmed in the "Page Write" section of the AT28LV64B-25PC datasheet and applies identically to the -25PC variant.
Does the AT28LV64B-25PC require external circuitry for write protection?
No, the AT28LV64B-25PC integrates both hardware- and software-based write protection. Hardware features include VCC power-on delay (~10 ms), noise filtering on WE/CE inputs (<15 ns rejection), and logic-level write inhibit. Software Data Protection (SDP) mandates a three-byte command sequence (AAh→55h→A0h) before any write-this mechanism is mandatory for all write operations on the AT28LV64B-25PC and eliminates need for external lock bits or hardware jumpers.
How is end-of-write detection implemented in the AT28LV64B-25PC?
The AT28LV64B-25PC provides two independent end-of-write detection methods: DATA polling on I/O7 (complement of last written byte until completion) and Toggle Bit on I/O6 (toggling between 0 and 1 until write finishes). Both methods are functional throughout the entire write cycle and do not require precise timing windows-engineers can poll at any interval. This dual-mode confirmation is documented in the "Device Operation" section of the AT28LV64B-25PC datasheet and verified across all package variants including PC.
What temperature ranges are supported by the AT28LV64B-25PC?
The AT28LV64B-25PC is rated for commercial temperature operation from 0°C to +70°C. This is explicitly specified in the "Ordering Information" table of the AT28LV64B datasheet, where the suffix "-25PC" denotes 250 ns speed grade and PDIP package with commercial temperature range. Industrial-grade variants (e.g., AT28LV64B-25PI) support -40°C to +85°C, but the -25PC variant is strictly commercial.
Is the AT28LV64B-25PC pin-compatible with standard 28-pin EPROMs like the 27C64?
Yes, the AT28LV64B-25PC uses a JEDEC-approved byte-wide pinout identical to industry-standard 28-pin EPROMs and EEPROMs, including the 27C64 and 28C64 families. Pin functions (A0–A12, I/O0–I/O7, CE, OE, WE, VCC, GND) match exactly in PDIP packaging. This allows direct PCB replacement in existing sockets without layout changes-confirmed in the "Pin Configurations" section of the AT28LV64B-25PC datasheet and validated across all 28P6 package variants.
AT28LV64B-25PC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-DIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-PDIP
AT28LV64B-25PC FAQ
1.How can I place an order for AT28LV64B-25PC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV64B-25PC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV64B-25PC reliable?
The price and inventory of AT28LV64B-25PC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV64B-25PC is usually 5 days.
3.What payment methods are accepted for AT28LV64B-25PC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV64B-25PC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV64B-25PC?
AT28LV64B-25PC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV64B-25PC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV64B-25PC?
For technical support, including AT28LV64B-25PC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV64B-25PC requirements.
6.How does Aetrix verify that AT28LV64B-25PC is sourced from the original manufacturer or authorized distributors?
All AT28LV64B-25PC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV64B-25PC meets industry standards.
7.What is the process for return or replacement of AT28LV64B-25PC?
All AT28LV64B-25PC units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV64B-25PC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV64B-25PC part is unused and in its original packaging.
Return procedure for AT28LV64B-25PC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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