Microchip Technology AT28LV64B-25SC
- Part No.:
- AT28LV64B-25SC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28LV64B-25SC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,576
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Product details
Overview
AT28LV64B-25SC from Atmel is a 64K-bit (8K × 8) parallel EEPROM with single 3.3V ±10% supply, 250 ns read access time, hardware/software data protection, and 64-byte page write capability. It operates across commercial temperature range (0°C to 70°C), supports JEDEC-standard byte-wide pinout, and delivers 15 mA active current with 20 µA CMOS standby current for low-power embedded nonvolatile storage.
For engineers reviewing the AT28LV64B-25SC datasheet, AT28LV64B-25SC pinout, AT28LV64B-25SC application, or AT28LV64B-25SC equivalent, key selection considerations include page-write timing (≤10 ms), DATA polling via I/O7, software data protection command sequence, and compatibility with static RAM-style bus interfacing in microcontroller systems.
Technical Context
The AT28LV64B-25SC implements a parallel interface with CE/OE/WE control logic enabling static RAM-like read/write cycles without external timing circuitry. Its internal 64-byte page register latches address and data during page writes, decoupling the host bus after initiation.
Write completion detection uses dual methods: DATA polling on I/O7 (complement-to-data → true-data transition) and toggle-bit behavior on I/O6. Software Data Protection requires a mandatory three-byte command sequence (0xAA→0x55→0xA0 at addresses 0x5555→0x2AAA→0x5555) before any write operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits); sufficient for firmware patch storage or configuration parameter tables in resource-constrained systems. |
| Read Access Time | 250 ns max; enables direct connection to 4–5 MHz microcontroller buses without wait states. |
| Page Write Cycle | ≤10 ms; allows burst programming of up to 64 bytes per cycle, reducing total write overhead vs. byte-by-byte. |
| Endurance | 100,000 write/erase cycles; supports field-upgradable systems requiring frequent reconfiguration. |
| Data Retention | 10 years at 25°C; ensures long-term reliability in unpowered storage applications like calibration data or serial numbers. |
| Supply Voltage | 3.3 V ±10%; compatible with modern low-voltage logic families and eliminates need for level-shifting in 3.3V systems. |
| Standby Current | 20 µA (CMOS); enables ultra-low-power retention in battery-backed or energy-harvesting devices. |
Pinout & Package
AT28LV64B-25SC is packaged in 28-lead SOIC (28S), JEDEC MS-012 compliant, 0.300" wide body with gull-wing leads. Pin 1 is index-marked; pins 1 and 28 are VCC and GND respectively.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte page writes. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit status during write cycles. |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; inhibits writes when high. |
| OE | Output Enable | Active-low output control; places I/O lines in high-impedance state when high, preventing bus contention. |
| WE | Write Enable | Active-low write strobe; initiates byte or page write when falling edge occurs with CE low and OE high. |
| NC | No Connect | Pins marked NC (e.g., SOIC pin 1, 28) are internally unconnected; must remain floating or tied to ground per layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection | Mandatory 3-byte unlock sequence prevents accidental writes during power-up/down or noise events-critical for field-deployed firmware integrity. |
| 64-byte Page Write | Reduces average write time by >90% vs. byte writes for contiguous data blocks, minimizing CPU bus occupancy in real-time systems. |
| DATA Polling (I/O7) | Enables asynchronous write completion detection without timers or interrupts-simplifies firmware design and improves determinism. |
| Hardware Write Inhibit | VCC power-on delay (~10 ms), noise filtering (<15 ns pulses rejected), and CE/OE/WE state locking prevent spurious writes under marginal supply conditions. |
| Device Identification Area | 64-byte reserved region (7FC0H–7FFFH) accessible at 12V on A9 for unique serialization or traceability without consuming main array space. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers subject to frequent field updates. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via 8-bit parallel bus during boot or maintenance mode; 250 ns read latency meets deterministic scan-cycle timing. Use Value: Page write reduces reconfiguration time from seconds to sub-100 ms; software data protection prevents corruption during brown-out events common in factory floor environments. |
Use Scenario: Retaining sensor calibration coefficients, device serial numbers, and usage logs in portable diagnostic equipment with battery backup. IC Role / Device Role / Timing Role: Low-power EEPROM providing tamper-resistant storage; 20 µA standby current extends battery life between calibrations. Use Value: 10-year data retention ensures compliance with medical device regulatory requirements; 12V-programmable ID area supports secure device authentication and traceability. |
| Automotive Body Control Module | Networking Equipment Bootloader Parameters |
Use Scenario: Saving seat/mirror position presets, lighting profiles, and error codes in automotive BCMs operating across -40°C to +85°C. IC Role / Device Role / Timing Role: Industrial-grade (SI variant) parallel EEPROM interfaced directly to MCU GPIO; JEDEC pinout simplifies PCB routing in space-constrained modules. Use Value: Hardware write inhibit prevents EEPROM corruption during vehicle ignition transients; endurance rating supports 10+ years of daily user adjustments. |
Use Scenario: Storing MAC address, firmware version flags, and network settings in Ethernet switches and routers requiring zero-downtime configuration changes. IC Role / Device Role / Timing Role: Configuration store accessed during boot and runtime; DATA polling allows concurrent packet processing while writing new settings. Use Value: Asynchronous write completion detection eliminates need for fixed delays-improves system responsiveness during remote management operations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-15PC | 5V-only supply (4.5–5.5V), 150 ns access, no software data protection, PDIP package only. | Lacks low-voltage operation and advanced write safeguards; suitable only for legacy 5V systems with simple write requirements. | Select only if existing 5V board lacks level-shifting and does not require field-safe write protection. |
| ST M28W640ECB90N6 | 3.3V supply, 90 ns access, 64K×8 organization, but uses SPI interface-not pin-compatible parallel interface. | Requires SPI controller and different firmware driver; incompatible with existing parallel bus designs without hardware redesign. | Choose only for new designs prioritizing speed and serial footprint reduction over backward compatibility. |
Compared with AT28LV64B-25SC, AT28C64B-15PC offers faster access but sacrifices low-voltage operation and data safety features, while ST M28W640ECB90N6 provides higher speed and smaller package but mandates interface redesign-neither is a drop-in replacement.
Availability
AT28LV64B-25SC is available at Aetrix Electronics and suitable for industrial automation, medical diagnostics, and automotive electronics requiring stable component supply, long-term manufacturability, and guaranteed data integrity under voltage fluctuation.
Supply support for AT28LV64B-25SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and security ICs for embedded systems.
The AT28LV64B product line was designed for reliable, low-voltage parallel EEPROM storage in industrial and automotive applications where robustness against power disturbances and long data retention are critical.
FAQ
What is the maximum operating temperature range for the AT28LV64B-25SC?
The AT28LV64B-25SC is rated for commercial temperature range: 0°C to +70°C. This is explicitly defined in the Ordering Information table for the "SC" suffix (SOIC, Commercial). It is not qualified for industrial (-40°C to +85°C) operation-those variants use the "SI" suffix (e.g., AT28LV64B-25SI).
Does the AT28LV64B-25SC support true 3.3V-only operation without 5V tolerance?
Yes. The AT28LV64B-25SC operates exclusively from a 3.3V ±10% supply (2.97V to 3.63V) and specifies all DC and AC parameters within that range. Input high voltage (VIH) is 2.0V min, and outputs are fully compatible with 3.3V CMOS logic-no 5V-tolerant inputs or mixed-voltage operation is supported.
How does software data protection work on the AT28LV64B-25SC?
The AT28LV64B-25SC requires a precise three-byte unlock sequence before any write: write 0xAA to address 0x5555, then 0x55 to 0x2AAA, then 0xA0 to 0x5555. Only after this sequence is completed can byte or page writes proceed. Without it, the device ignores data and enters polling mode for tWC (10 ms), ensuring no accidental writes occur.
Can the AT28LV64B-25SC be used as a direct replacement for standard SRAM in a system?
No. While the AT28LV64B-25SC uses SRAM-like read timing and bus protocol, it is not a true SRAM replacement due to write latency (up to 10 ms per page), mandatory unlock sequences, and non-volatile behavior. It cannot support random write cycles at SRAM speeds and requires explicit write-enable control and status polling.
What package type does the AT28LV64B-25SC use, and are there lead-free options?
The AT28LV64B-25SC uses a 28-lead SOIC (28S) package, 0.300" wide, with gull-wing leads. Per Atmel's packaging documentation and ordering table, the "SC" suffix denotes SOIC Commercial; RoHS-compliant (lead-free) versions were introduced later under revised part numbering (e.g., AT28LV64B-25SCU), but the base AT28LV64B-25SC is leaded unless otherwise specified.
AT28LV64B-25SC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28LV64B-25SC FAQ
1.How can I place an order for AT28LV64B-25SC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV64B-25SC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV64B-25SC reliable?
The price and inventory of AT28LV64B-25SC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV64B-25SC is usually 5 days.
3.What payment methods are accepted for AT28LV64B-25SC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV64B-25SC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV64B-25SC?
AT28LV64B-25SC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV64B-25SC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV64B-25SC?
For technical support, including AT28LV64B-25SC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV64B-25SC requirements.
6.How does Aetrix verify that AT28LV64B-25SC is sourced from the original manufacturer or authorized distributors?
All AT28LV64B-25SC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV64B-25SC meets industry standards.
7.What is the process for return or replacement of AT28LV64B-25SC?
All AT28LV64B-25SC units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV64B-25SC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV64B-25SC part is unused and in its original packaging.
Return procedure for AT28LV64B-25SC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28LV64B-25SC Tags

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