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Microchip Technology AT28LV64B-25SI
- Part No.:
- AT28LV64B-25SI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28LV64B-25SI.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:3,150
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Product details
Overview
AT28LV64B-25SI from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with 3.3 V ±10% single-supply operation, 250 ns read access time, and hardware/software data protection. It supports page write (1–64 bytes), DATA polling (I/O7), and toggle-bit (I/O6) write completion detection for embedded control and firmware storage applications.
For engineers reviewing the AT28LV64B-25SI datasheet, AT28LV64B-25SI pinout, AT28LV64B-25SI application, or AT28LV64B-25SI equivalent, key selection considerations include JEDEC byte-wide pin compatibility, industrial temperature range (–40°C to +85°C), CMOS standby current (≤50 µA), and software data protection command sequence requirements.
Technical Context
The AT28LV64B-25SI operates as a drop-in parallel memory replacement for SRAM or EPROM in legacy 8-bit bus systems, using standard CE/OE/WE control logic without external timing components. Its internal 64-byte page register latches address and data during page write, enabling burst loading within 100 µs inter-byte intervals.
Write completion is verified via two independent methods: DATA polling on I/O7 (complement-to-data during write, true data after completion) and toggle-bit behavior on I/O6 (toggling until write ends). Both mechanisms eliminate need for fixed delay timers in host firmware.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits); sufficient for boot code, calibration tables, or configuration data in microcontroller-based systems. |
| Read Access Time | 250 ns max; compatible with 4 MHz Z80, 8051, and 68K bus cycles without wait states. |
| Page Write Cycle | 10 ms max; enables efficient bulk updates of up to 64 bytes per internal programming operation. |
| Supply Voltage | 3.3 V ±10%; eliminates level-shifting when interfacing with modern low-voltage MCUs and FPGAs. |
| Standby Current | 50 µA max (industrial temp); supports ultra-low-power retention in battery-backed or energy-harvesting systems. |
| Endurance | 100,000 write/erase cycles; suitable for field-upgradable firmware or infrequently modified system parameters. |
| Data Retention | 10 years at +85°C; ensures long-term reliability in automotive and industrial control environments. |
Pinout & Package
AT28LV64B-25SI is packaged in a 28-lead SOIC (28S) with JEDEC-standard byte-wide pinout. Pin functions are electrically identical across PDIP, SOIC, TSOP, and PLCC variants; SOIC variant uses gull-wing leads for surface-mount assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus; selects one of 8,192 memory locations (A0 = LSB, A12 = MSB). |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; drives outputs during read, accepts inputs during write, high-Z when deselected. |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read access; inhibits writes when high. |
| OE | Output Enable | Active-low output control; places I/O pins in high-impedance state when high, preventing bus contention. |
| WE | Write Enable | Active-low write strobe; initiates byte or page write on falling edge; requires SDP command sequence first. |
| VCC | Power Supply | +3.3 V ±10% supply; powers core logic and memory array; internal power-on delay prevents spurious writes. |
| GND | Ground Reference | Signal and power return path; decoupling capacitor required within 10 mm of VCC pin. |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Three-step command sequence (AAh→55h→A0h at specific addresses) required before every write; prevents corruption during power transitions. |
| Hardware Write Inhibit | Automatic 10 ms VCC power-on delay + noise filtering (<15 ns pulses rejected) + dual-line control (CE/OE/WE logic) blocks accidental writes. |
| Page Write Mode | Internal 64-byte latch allows sequential loading of 1–64 bytes within 100 µs intervals; frees address/data bus for other tasks during load phase. |
| DATA Polling & Toggle Bit | Dual asynchronous write-complete detection: I/O7 returns complement until done; I/O6 toggles until done-enables interrupt-driven or polling-based host firmware. |
| Device Identification Area | 64-byte reserved region (7FC0h–7FFFh) accessible at 12 V on A9; supports unique serialization, calibration data, or manufacturing traceability. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via 8-bit parallel bus during startup and runtime parameter updates. Use Value: 100,000-cycle endurance and 10-year data retention ensure reliable operation over 15+ year equipment lifecycles without battery backup. | Use Scenario: Holding sensor calibration coefficients, device serial numbers, and regulatory compliance flags in portable diagnostic instruments. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage with hardware/software write protection to meet IEC 62304 safety requirements. Use Value: SDP command sequence and 12 V–enabled ID area prevent unauthorized firmware modification and support audit-ready device traceability. |
| Automotive Body Control Module (BCM) | Telecom Line Card Firmware Patch Storage |
Use Scenario: Saving seat/mirror position presets, lighting profiles, and fault logs in automotive BCMs operating across –40°C to +85°C. IC Role / Device Role / Timing Role: Industrial-grade parallel EEPROM interfaced directly to 8051 or PIC MCU without glue logic. Use Value: 50 µA standby current extends battery life during vehicle sleep mode; 250 ns access supports real-time response to CAN bus commands. | Use Scenario: Storing hot-swappable firmware patches and configuration overrides for carrier-grade DSLAM line cards requiring zero-downtime updates. IC Role / Device Role / Timing Role: Field-upgradable nonvolatile memory supporting atomic page writes to avoid partial-update corruption. Use Value: 10 ms page write cycle enables sub-100 ms patch application; DATA polling allows deterministic host synchronization without fixed delays. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECT | 64 Mbit (8M × 8), 3.3 V, 120 ns access, no software data protection; requires external write enable control. | Higher density but lacks SDP and page-write automation; suited for high-speed boot ROM, not parameter storage. | Select only if >64 Kbit capacity and <120 ns timing are mandatory; verify absence of SDP does not compromise system safety. |
| Microchip 25LC640A-I/SN | 64 Kbit SPI EEPROM, 2.5–5.5 V, 5 ms write cycle, software write protect; serial interface replaces parallel bus. | Reduces pin count and PCB area but adds SPI protocol overhead; incompatible with existing parallel-addressed designs. | Choose for new designs prioritizing layout simplicity and lower I/O count; not a drop-in replacement for AT28LV64B-25SI's parallel interface. |
Compared with ST M28W640ECT and Microchip 25LC640A-I/SN, the AT28LV64B-25SI uniquely combines JEDEC byte-wide pinout, integrated page-write logic, and dual-layer (hardware + software) data protection-making it irreplaceable in legacy parallel-bus systems requiring robust, field-upgradable nonvolatile storage.
Availability
AT28LV64B-25SI is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, automotive body control modules, and telecom line cards requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for AT28LV64B-25SI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) designed high-reliability nonvolatile memory and microcontrollers for industrial, automotive, and communications markets.
The AT28LV64B product line delivers low-voltage, page-write-capable parallel EEPROMs optimized for firmware storage, configuration retention, and calibration data logging in resource-constrained embedded systems.
FAQ
What is the operating temperature range for the AT28LV64B-25SI?
The AT28LV64B-25SI is rated for industrial temperature operation from –40°C to +85°C. This range is confirmed in the "DC and AC Operating Range" table of the datasheet and applies specifically to part numbers ending in 'I' (e.g., -25SI). It ensures reliable read/write functionality in harsh environments such as factory floors or under-hood automotive applications where thermal stability is critical. The AT28LV64B-25SI maintains full specification compliance-including 250 ns read access and ≤50 µA standby current-across this entire range.
Does the AT28LV64B-25SI require external circuitry for write operations?
No, the AT28LV64B-25SI performs autonomous write cycles without external timing components. Once the software data protection (SDP) command sequence is issued and a write is initiated via WE or CE, the internal control timer manages the full 10 ms page write or byte write sequence. The device automatically latches addresses and data, then executes programming internally. Host systems only need to monitor I/O7 (DATA polling) or I/O6 (toggle bit) to detect completion-no external clocks, RC networks, or state machines are required. This simplifies design and improves reliability compared to older EEPROMs needing external write-enable pulse generation.
How does software data protection (SDP) work on the AT28LV64B-25SI?
Software data protection on the AT28LV64B-25SI requires a precise three-byte command sequence before any write: write 0xAA to address 0x5555, then 0x55 to address 0x2AAA, then 0xA0 to address 0x5555. This sequence must be repeated before each byte or page write operation. The AT28LV64B-25SI validates the sequence in real time; failure to deliver it results in no data being written, though internal write timers still activate (causing subsequent reads to behave as polling operations for tWC duration). This mechanism prevents corruption during power-up/down transients or noise-induced glitches on the bus-critical for systems where firmware integrity is safety-critical.
Can the AT28LV64B-25SI be used as a direct replacement for older 5 V EEPROMs?
No, the AT28LV64B-25SI is not a direct replacement for 5 V EEPROMs due to its strict 3.3 V ±10% supply requirement and incompatible input voltage thresholds (VIH = 2.0 V, VIL = 0.6 V). Interfacing with 5 V logic buses requires level translation on all control and data lines (CE, OE, WE, I/O0–I/O7). Additionally, its software data protection command sequence differs from legacy 5 V devices like the AT28C64B. While pinout is JEDEC-compatible, electrical and protocol-level incompatibility means board-level redesign-including voltage regulation and signal conditioning-is necessary for migration from 5 V to AT28LV64B-25SI.
What package type does the AT28LV64B-25SI use, and is it RoHS compliant?
The AT28LV64B-25SI uses a 28-lead, 0.300" wide plastic gull-wing small outline integrated circuit (SOIC) package, designated as '28S' in Atmel's ordering information. This surface-mount package is compatible with standard reflow soldering processes. Regarding RoHS compliance: while the original Atmel datasheet (Rev. 1683AX–07/00, 2000) predates RoHS legislation, Microchip Technology's current product change notices confirm that legacy AT28LV64B variants-including AT28LV64B-25SI-are manufactured in RoHS-compliant, lead-free versions. Aetrix Electronics supplies only RoHS-compliant units meeting J-STD-609 Category 1 marking requirements.
AT28LV64B-25SI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28LV64B-25SI FAQ
1.How can I place an order for AT28LV64B-25SI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV64B-25SI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV64B-25SI reliable?
The price and inventory of AT28LV64B-25SI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV64B-25SI is usually 5 days.
3.What payment methods are accepted for AT28LV64B-25SI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV64B-25SI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV64B-25SI?
AT28LV64B-25SI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV64B-25SI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV64B-25SI?
For technical support, including AT28LV64B-25SI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV64B-25SI requirements.
6.How does Aetrix verify that AT28LV64B-25SI is sourced from the original manufacturer or authorized distributors?
All AT28LV64B-25SI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV64B-25SI meets industry standards.
7.What is the process for return or replacement of AT28LV64B-25SI?
All AT28LV64B-25SI units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV64B-25SI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV64B-25SI part is unused and in its original packaging.
Return procedure for AT28LV64B-25SI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28LV64B-25SI Tags
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M24C02-WMN6TP
STMicroelectronics
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AT24C02C-XHM-T
Microchip Technology
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AT21CS01-STUM10-T
Microchip Technology
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AT24C02C-SSHM-T
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24LC01BT-I/OT
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M24C02-FMC6TG
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AT24CS02-SSHM-T
Microchip Technology
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93LC46BT-I/OT
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AT24C04C-SSHM-T
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24LC01BT-I/SN
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24AA02UIDT-I/OT
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AT24C08C-STUM-T
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